PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 202
PC87307VUL
Manufacturer Part Number
PC87307VUL
Description
PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
Manufacturer
National Semiconductor
Datasheet
1.PC87307VUL.pdf
(218 pages)
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13.3.11 DMA Timing
t
t
t
t
t
t
t
t
t
t
t
t
KI
KK
KQ
QK
QP
QQ
QR
QW
QT
RQ
TQ
TT
Symbol
a. t
b. Only in case of pending DRQ.
c. Values shown are with the FIFO disabled, or with FIFO enabled and THRESH = 0. For nonzero values of
d. The active edge of RD or WR and TC is recognized only when DACK is active.
THRESH, add (THRESH x 8 x t
DRQ
DACK
RD, WR
TC
DRP
DACK Inactive Pulse Width
DACK Active Pulse Width
DACK Active Edge to DRQ Inactive
DRQ to DACK Active Edge
DRQ Period (Except Non-Burst DMA)
DRQ Inactive Non-Burst Pulse Width
DRQ to RD, WR Active
DRQ to End of RD, WR (DRQ Service Time)
DRQ to TC Active (DRQ Service Time)
RD, WR Active Edge to DRQ Inactive
TC Active Edge to DRQ Inactive
TC Active Pulse Width
and t
ICP
t
QK
are defined in Table 13-36.
Parameter
t
QT
t
QR
DRP
) to the values shown.
FIGURE 13-15. FDC DMA Timing
TABLE 13-45. FDC DMA Timing
Device Description
d
t
QW
202
t
KK
t
t
TT
KQ
8 x t
t
t
QP
TQ
Min
300
t
25
65
10
15
50
RQ
DRP
a
(8 x t
(8 x t
DRP
DRP
)
)
400
Max
65
65
75
(16 x t
(16 x t
b
ICP
ICP
t
KI
t
QQ
)
)
a c
a c
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
Unit
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