PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 123

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Reading from this register pops a byte from the FIFO. Writ-
ing to this register when it is set for read-only has no effect,
and the data written is ignored.
6.5.9
A byte written into the Test FIFO (TFIFO) register is pushed
into the FIFO. A byte read from this register is popped from
the FIFO. The ECP does not issue an ECP cycle to transfer
the data to or from the peripheral device.
The TFIFO is readable and writable in both directions. In the
forward direction (bit 5 of DCR is 0) PD7-0 are driven, but
the data is undefined.
The FIFO does not stall when overwritten or underrun (ac-
cess is ignored). Bytes are always read from the top of the
FIFO, regardless of the direction bit setting (bit 5 of DCR).
For example if 44h, 33h, 22h, 11h is written into the FIFO,
reading the FIFO returns 44h, 33h, 22h, 11h (in the same
order it was written).
0
0
7
7
D7
D7
0
0
6
6
Test FIFO (TFIFO) Register,
Bits 7-5 of ECR = 110, Offset 400h
FIGURE 6-22. DFIFO Register Bitmap
D6
D6
FIGURE 6-23. TFIFO Register Bitmap
0
0
5
5
D5
D5
0
0
4
4
D4
D4
0
0
3
3
Bits 7-5 of ECR = 011
Bits 7-5 of ECR = 110
D3
D3
0
0
2
2
Data Bits
Data Bits
D2
D2
0
0
1
1
D1
D1
0
0
0
0
D0
D0
Reset
Required
Reset
Required
Register (DFIFO)
Register (TFIFO)
ECP Data FIFO
Parallel Port (Logical Device 4)
Offset 400h
Offset 400h
Test FIFO
123
6.5.10 Configuration Register A (CNFGA),
This register is read only. Reading CNFGA always returns
100 on bits 2 through 0 and 0001 on bits 7 through 4.
Writing this register has no effect and the data is ignored.
Bits 2-0 - Reserved
Bit 3 - Bit 7 of PP Confg0
Bit 7-4 - Reserved
6.5.11 Configuration Register B (CNFGB), Bits 7-5 of
Configuration register B (CNFGB) is read only. Reading this
register returns the configured parallel port interrupt line
and DMA channel, and the state of the interrupt line.
Writing to this register has no effect and the data is ignored.
0
0
0
7
7
These bits are reserved and are always 100.
This bit reflects the value of bit 7 of the ECP PP Confg0
register (second level offset 05h), which has no specific
function. Whatever value is put in bit 7 of PP Confg0 will
appear in this bit.
This bit reflects a specific system configuration parame-
ter, as opposed to other devices, e.g., 8-bit data word
length.
These bits are reserved and are always 0001.
Always 0
Reserved
0
0
0
6
6
FIGURE 6-24. CNFGA Register Bitmap
FIGURE 6-25. CNFGB Register Bitmap
Bits 7-5 of ECR = 111, Offset 400h
ECR = 111, Offset 401h
IRQ Signal Value
Always 0
x
0
0
5
5
Always 0
x
1
1
4
4
Always 1
x
0
3
3
Bits 7-5 of ECR = 111
Bits 7-5 of ECR = 111
Interrupt Select
Bit 7 of PP Confg0
1
1
0
2
2
Always 1
Reserved
0
0
0
1
1
Always 0
0
0
0
0
0
DMA Channel Select
Configuration Register B
Configuration Register A
Reset
Required
Reset
Required
Always 0
Offset 401h
Offset 400h
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(CNFGA)
(CNFGB)