PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 204

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PC87307VUL

Manufacturer Part Number
PC87307VUL
Description
PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
Manufacturer
National Semiconductor
Datasheet
www.national.com
13.3.12 Reset Timing
Note:
13.3.13 Write Data Timing
In PC-AT mode, the DRQ and IRQ signals of the FDC are in TRI-STATE after time t
WDATA
HDSEL
WGATE
MR
DRQ,
INT,
WGATE (Note)
t
t
t
t
t
HDH
HDS
WDW
RW
SRC
Symbol
Symbol
a. Not tested. Guaranteed by design.
a. The software reset pulse width is 100 nsec.
b. Not tested. Guaranteed by design.
a. t
HDSEL Hold from WGATE Inactive
HDSEL Setup to WGATE Active
Write Data Pulse Width
Reset Width
Reset to Control Inactive
ICP
t
HDS
Data Rate
500 Kbps
300 Kbps
250 Kbps
1 Mbps
is the internal clock period defined in Table 13-36.
TABLE 13-49. Write Data Timing – Minimum t
a
Parameter
Parameter
FIGURE 13-18. Write Data Timing
TABLE 13-48. Write Data Timing
FIGURE 13-17. Reset Timing
TABLE 13-47. Reset Timing
b
Device Description
1000
2000
3333
4000
t
t
WDW
DRP
t
a
RW
a
t
204
SRC
2 x t
2 x t
2 x t
2 x t
t
WDW
ICP
ICP
ICP
ICP
Table 13-49
a
a
a
a
Min
100
Min
750
100
WDW
t
WDW
250
250
375
500
Values
Value
SRC
.
Max
Max
300
nsec
nsec
nsec
nsec
t
Unit
HDH
nsec
Unit
Unit
sec
sec
sec

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