PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 16

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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CFG3-0
CS0
CS2,1
CSOUT-
NSC-Test
CTS2,1
D7-0
DACK3-0
DCD2,1
DENSEL
Signal/Pin
Name
148, 146,
144, 138
68
68
141, 131
10-3
59-56
142, 132
94
72, 71
Number
Pin
Configuration
NSC use
Purpose
Purpose
ISA-Bus
ISA-Bus
General
General
UART1,
UART1,
Module
UART2
UART2
FDC
Signal/Pin Connection and Description
Group 21
Group 21
Group 16
Group #
Group 5
Group 9
Group 1
Group 8
Group 1
Group 1
I/O and
Output
Output
Output
Input
Input
Input
Input
I/O
I/O
Configuration Strap Pins 3-0 – These pins determine the default
configuration upon power up. These pins are pulled down by internal
30 K
employed.
CFG3 is multiplexed with SOUT2. CFG2 is multiplexed with RTS2.
CFG1 is multiplexed with DTR2 and BOUT2. CFG0 is multiplexed
with SOUT1. See Table 2-2 on page 25 and Section 2.1 on page 24
for more information.
Programmable Chip Select – CS0, CS1 and CS2 are
programmable chip select and/or latch enable and/or output enable
signals that have many uses, for example, as game ports or for I/O
port expansion.
The decoded address and the assertion conditions are configured via
the chip configuration registers. See Section 2.3 on page 26.
CS0 is an open-drain pin that is in TRI-STATE unless V
CS2 is multiplexed with XD1, CS1 is multiplexed with XD0, and CS0
is multiplexed with CSOUT-NSC-Test.
Chip Select Read Output, NSC-Test – National Semiconductor test
output. This is an open-drain output signal.
This signal is multiplexed with CS0.
UART1 and UART2 Clear to Send – When low, these signals indicate
that the modem or other data transfer device is ready to exchange data.
The CTS signal is a modem status input signal whose condition the
CPU can test by reading bit 4 (CTS) of the Modem Status Register
(MSR) for the appropriate serial channel. Bit 4 is the complement of the
CTS signal. Bit 0 (DCTS) of MSR indicates whether the CTS input signal
has changed state since the previous reading of MSR. CTS has no
effect on the transmitter.
Whenever the DCTS bit of the MSR is set, an interrupt is generated
if modem status interrupts are enabled.
ISA-Bus Data – Bidirectional data lines to the microprocessor. D0 is
the LSB and D7 is the MSB. These signals have 24 mA (sink)
buffered outputs.
DMA Acknowledge 0,1,2 and 3 – These active low input signals
acknowledge a request for DMA services and enable the IOWR and
IORD input signals during a DMA transfer. These DMA signals can
be mapped to the following logical devices: FDC, UART1, UART2 or
parallel port.
UART1 and UART2 Data Carrier Detected – When low, this signal
indicates that the modem or other data transfer device has detected
the data carrier.
The DCD signal is a modem status input signal whose condition the
CPU can test by reading bit 7 (DCD) of the Modem Status Register
(MSR) for the appropriate serial channel. Bit 7 is the complement of
the DCD signal.
Bit 3 (DDCD) of the MSR indicates whether the DCD input signal has
changed state since the previous reading of MSR. Whenever the
DDCD bit of the MSR is set, an interrupt is generated if modem
status interrupts are enabled.
Density Select (FDC) – Indicates that a high FDC density data rate
(500 Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps)
is selected.
DENSELs polarity is controlled by bit 5 of the SuperI/O FDC
Configuration register as described in Section 2.6.1 on page 36.
resistors. External 10 K
16
Function
pull-up resistors to V
DD
DD
should be
is applied.