PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 54

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
4.2.2
This register enables the selection of various time and date
options, as well as the use of interrupts.
Bit 1 - 24 or 12 Hour Mode
Bit 2 - Data Mode (DM)
Bit 3 - Unused
Bit 4 - Update-Ended Interrupt Enable (UIE)
Bit 5 - Alarm Interrupt Enable (AIE)
Bit 0 - Daylight Savings Enable (DSE)
7
Master reset does not affect this read/write bit.
0 - Disables the daylight savings feature.
1 - Enables daylight savings feature, as follows:
This is a read/write bit that is not affected by reset.
0 - Enables 12 hour format.
1 - Enables 24 hour format.
This is a read/write bit that is not affected by reset.
0 - Enables BCD format.
1 - Enables binary format.
This bit is defined as “Square Wave Enable” by the
MC146818 and is not supported by the RTC. This bit is
always read as 0.
Master reset forces this read/write bit to 0.
0 - Disables generation of the Update-Ended interrupt.
1 - Enables generation of the Update-Ended interrupt.
Master reset forces this read/write bit to 0.
0 - Disables generation of the alarm interrupt.
1 - Enables generation of the Alarm interrupt. The
SET
6
0
In the spring, time advances from 1:59:59 to
3:00:00 on the first Sunday in April.
In the fall, time returns from 1:59:59 to 1:00:00 on
the last Sunday in October.
This interrupt is generated at the time an update
occurs.
alarm interrupt is generated immediately after a
time update in which the Seconds, Minutes, and
Hours time equal their respective alarm counter-
parts.
PIE
RTC Control Register B (CRB), Index 0Bh
5
0
FIGURE 4-6. CRB Register Bitmap
AIE
4
0
3
0
0
UIE
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Unused
2
DM
1
24 or 12 Hour Mode
0
Power-Up
Reset
Required
DSE
RTC Control
Register B
Index 0Bh
(CRB)
54
Bit 6 - Periodic Interrupt Enable (PIE)
Bit 7 - Set Mode (SET)
4.2.3
This register indicates the status of interrupt request flags.
Bits 3-0 - Reserved
Bit 4 - Update-Ended Interrupt Flag (UF)
Bit 5 - Alarm Interrupt Flag (AF)
Bit 6 - Periodic Interrupt Flag (PF)
7
Master reset forces this read/write bit to 0.
0 - Disables generation of the Periodic interrupt.
1 - Enables generation of the Periodic interrupt. Bits 3-
Master reset does not affect this read/write bit.
1 - The user copy of time is “frozen”, allowing the time
These bits are reserved and always return 0000.
Master reset forces this read-only bit to 0. In addition,
this bit is reset to 0 when this register is read.
0 - No update has occurred since the last read.
1 - Time registers have been updated.
Master reset forces this read-only bit to 0.
0 - No alarm was detected since the last read.
1 - An alarm condition was detected. This bit is reset to
Master reset forces this read-only bit to 0. In addition,
this bit is reset to 0 when this register is read.
0 - Indicates no transition occurred on the selected tap
1 - A transition occurred on the selected tap of the di-
0 - The timing updates occur normally.
IRQF
6
0
0 of Control Register A (CRA) determine the rate of
the Periodic interrupt.
registers to be accessed without regard for an oc-
currence of an update.
0 when this register is read.
since the last read.
vider chain.
RTC Control Register C (CRC), Index 0Ch
PF
5
0
FIGURE 4-7. CRC Register Bitmap
AF
4
0
UF
3
0
0
2
0
0
1
0
0
Reserved
0
0
0
Power-Up
Reset
Required
RTC Control
Register C
Index 0Ch
(CRC)