PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 130

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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ECP (Backward) Read Cycle
An ECP read cycle starts when the ECP drives AFD low.
The peripheral device drives BUSY high for a normal data
read cycle, or drives BUSY low for a command read cycle,
and drives the byte to be read onto PD7-0.
When ACK is asserted the ECP drives AFD high. When
AFD is high the peripheral device deasserts ACK. The ECP
reads the PD7-0 byte, then drives AFD low. When AFD is
low the peripheral device may change BUSY and PD7-0
states in preparation for the next cycle
.
Notes:
1. FIFO-full condition is checked before every expanded
2. Switching from modes 010 or 011 to other modes re-
3. FIFO pushes and pops are neither synchronized nor
4. In the forward direction, the empty bit is updated when
5. ZWS is not asserted for DMA cycles.
6. The one-bit command/data tag is used only in the for-
6.6.3
Automatic address and data transfer (EPP cycles generat-
ed by hardware) is supported in mode 100. Fast transfers
are achieved by automatically generating the address and
data strobes.
In this mode, the FIFO is reset (empty) and is not functional,
the DMA and RLE are idle.
The direction of the automatic data transfers is determined
by the RD and WR signals. The direction of software data
transfer can be forward or backward, depending on bit 5 of
the DCR. Bit 5 of the DCR determines the default direction
of the data transfers only when there is no on-going EPP cy-
cles.
In EPP mode 100, registers DATAR, DSR and DCR are
used instead of DTR, STR and CTR respectively.
PD7-0
BUSY
byte push.
moves pending DMA requests and aborts pending RLE
expansion.
linked at the hardware level. The FIFO will not delay
these operations, even if performed concurrently. Care
must be taken by the programmer to utilize the empty
and full FIFO status bits to avoid corrupting PD7-0 or
D7-0 while a previous FIFO port access not complete.
the ECP cycle is completed, not when the last byte is
popped from the FIFO (valid cleared on cycle end).
ward direction.
AFD
ACK
FIGURE 6-35. ECP (Backward) Read Cycle
Automatic Address and Data Transfers
(Mode 100)
Parallel Port (Logical Device 4)
130
Some differences are caused by the registers. Reading DA-
TAR returns pins values instead of register value returned
when reading DTR. Reading DSR returns register value in-
stead of pins values returned when reading STR. Writing to
the DATAR during an on-going EPP 1.9 forward cycle (i.e.
- when bit 7 of DSR is 1) causes the new data to appear im-
mediately on PD7-0, instead of waiting for BUSY to become
low to switch PD7-0 to the new data when writing to the
DTR.
In addition, the bit 4 of the DCR functions differently relative
to bit 4 of the CTR (IRQ float).
6.6.4
Mode 110 is for testing the FIFO in PIO and DMA cycles.
Both read and write operations (pop and push) are support-
ed, regardless of the direction bit.
In the forward direction PD7-0 are driven, but the data is un-
defined. This mode can be used to measure the system-
ECP cycle throughput, usually with DMA cycles. This mode
can also be used to check the FIFO depth and its interrupt
threshold, usually with PIO cycles.
6.6.5
The two configuration registers, CNFGA and CNFGB, are
accessible only in this mode.
6.6.6
An interrupt is generated when any of the events described
in this section occurs. Interrupt events 2, 3 and 4 are level
events. They are shaped as interrupt pulses, and are
masked (inactive) when the ECP clock is frozen.
Event 1
Event 2
Event 3
Event 4
Event 5
Bit 2 of ECR is 0, bit 3 of ECR is 1 and TC is asserted
during ECP DMA cycle. Interrupt event 1 is a pulse
event.
Bit 2 of ECR is 0, bit 3 of ECR is 0, bit 5 of DCR is 0 and
there are eight or more bytes free in the FIFO.
This event includes the case when bit 2 of ECR is
cleared to 0 and there are already eight or more bytes
free in the FIFO (modes 010, 011 and 110 only).
Bit 2 of ECR is 0, bit 3 of ECR is 0, bit 5 of DCR is 1 and
there are eight or more bytes to be read from the FIFO.
This event includes the case when bit 2 of ECR is
cleared to 0 and there are already eight or more bytes
to be read from the FIFO (modes 011 and 110 only).
Bit 4 of ECR is 0 and ERR is asserted (high to low edge)
or ERR is asserted when bit 4 of ECR is modified from
1 to 0.
This event may be lost when the ECP clock is frozen.
When bit 4 of DCR is 1 and ACK is deasserted (low-to-
high edge).
This event behaves as in the normal SPP mode, i.e., the
IRQ signal follows the ACK signal transition.
FIFO Test Access (Mode 110)
Configuration Registers Access (Mode 111)
Interrupt Generation