PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 35

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Bit 0 - ZWS Enable
Bit 1 - CSOUT-NSC-test or CS0 Pin Select
Bit 2 - PC-AT or PS/2 Drive Mode Select
Bit 3 - Reserved
Bit 4 - X-Bus Data Buffer (XDB) Select
Bit 5 - Lock Scratch Bit
Bits 7,6 - General Purpose Scratch Bits
2.4.4
This read/write register is reset by hardware to 00h-03h.
See BADDR1,0 strap pins in Section 2.1.3.
FIGURE 2-4. SuperI/O Configuration 2 Register Bitmap
0
7
This bit controls assertion of ZWS on any host SuperI/O
chip access, except for configuration registers access
(including Serial Isolation register) and except for Paral-
lel Port access.
For ZWS assertion on host-EPP access, see Section
6.5.17 on page 126.
0 - ZWS is not asserted.
1 - ZWS is asserted.
This bit is initialized with SELCS strap value.
0 - CSOUT-NSC-test on CS0 pin.
1 - CS0.
0 - PS/2 drive mode.
1 - PC-AT drive mode. (Default)
Reserved.
Select X-bus buffer on the XDB pins. This read only bit
is initialized with the CFG1 strap value. See also Chap-
ter 10 on page 179.
0 - No XDB buffer. XDB pins have alternate function,
1 - XDB enabled.
This bit controls bits 7 and 6 of this register. Once this
bit is set to 1 by software, it can be cleared to 0 only by
a hardware reset.
0 - Bits 7 and 6 of this register are read/write bits.
1 - Bits 7 and 6 of this register are read only bits.
When bit 5 is set to 1, these bits are read only. After re-
set they can be read or written. Once changed to read-
only, they can be changed back to be read/write bits
only by a hardware reset.
GPIO Bank Select
0
6
see Table 1-2 on page 23.
SuperI/O Configuration 2 Register, Index 22h
GPIO17 or WDO Pin Select
0
5
GPIO20 or IRSL1 Pin Select
0
4
0
3
GPIO21, IRSL2/ ID2 or ISL0 Pin Select
0
2
GPIO22 or POR Select
x
1
x
0
SuperI/O Configuration 2
Reset
Required
BADDR1 and BADDR0
Index 22h
Register,
Configuration
35
Bits 1,0 - BADDR1 and BADDR0
Bit 2 - GPIO22 or POR Pin Select
Bits 4,3 - GPIO21, IRSL2/ID2 or IRSL0 Pin Select
Bit 5 - GPIO20, IRSL1 or ID1 Pin Select
Bit 6 - GPIO17 or WDO Pin Select
Bit 7 - GPIO Bank Select
2.4.5
This read/write register is reset by hardware to 00h. It indi-
cates the index of one of the Programmable Chip Select
(CS0, CS1 or CS2) configuration registers described in
Section 2.10.
The data in the indicated register is in the Programmable
Chip Select Configuration Data register at index 24h.
Bits 7 through 4 are read only and return 0000 when read.
4 3
0 0
0 1
1 0
1 1
TABLE 2-21. Signal Assignment for Pins 158 and 77
Bit
Initialized on reset by BADDR1 and BADDR0 strap pins
(BADDR0 on bit 0). These bits select the addresses of
the configuration Index and Data registers and the Plug
and Play ISA Serial Identifier. See Tables 2-1 and 2-2.
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers.
0 - The pin is GPIO22.
1 - The pin is POR.
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers as shown in
Table 2-21.
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers.
0 - The pin is GPIO20.
1 - The pin is IRSL1/ID1.
This bit determines whether GPIO17 or WDO is routed
to pin 156 when bit 7 of the Port 1 Direction register at
offset 01h of logical device 7 is set to 1. See Section 8.1
on page 170.
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers.
0 - GPIO17 uses the pin. (Default)
1 - WDO uses the pin.
This bit selects the active register ban1k of GPIO regis-
ters.
0 - Bank 0 is selected. (Default)
1 - Bank 1 is selected.
IRSL2/ID2
Reserved
Programmable Chip Select Configuration Index
Register, Index 23h
Pin 158
GPIO21
IRSL0
Pin 77 when Bit 4 of SuperI/O
Config 1 Register = 0
GPIO21/SELCS
IRSL2/SELCS
IRSL2/SELCS
IRSL2/SELCS
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