PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 146

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
Link Control Register (LCR), All Banks, Offset 03h
Bits 6-0 are only effective in UART, Sharp-IR and SIR
modes. They are ignored in Consumer-IR mode.
Bits 1,0 - Character Length Select (WLS1,0)
Bits 2 - Number of Stop Bits (STB)
Bit 3 - Parity Enable (PEN)
Bit 4 - Even Parity Select (EPS)
0
7
These bits specify the number of data bits in each trans-
mitted or received serial character. Table 7-7 shows
how to encode these bits.
This bit specifies the number of stop bits transmitted
with each serial character.
0 - One stop bit is generated. (Default)
1 - If the data length is set to 5-bits via bits 1,0
This bit enable the parity bit See Table 7-8 on page 146.
The parity enable bit is used to produce an even or odd
number of 1s when the data bits and parity bit are
summed, as an error detection device.
0 - No parity bit is used. (Default)
1 - A parity bit is generated by the transmitter and
When Parity is enabled (PEN is 1), this bit, together with
bit 5 (STKP), controls the parity bit as shown in Table
7-8.
0 - If parity is enabled, an odd number of logic 1s are
WLS1
0
6
BKSE
TABLE 7-7. Word Length Select Encoding
(WLS1,0), 1.5 stop bits are generated. For 6, 7 or 8
bit word lengths, two stop bits are transmitted. The
receiver checks for one stop bit only, regardless of
the number of stop bits selected.
checked by the receiver.
transmitted or checked in the data word bits and
parity bit. (Default)
0
0
1
1
SBRK
0
5
FIGURE 7-11. LCR Register Bitmap
0
4
STKP
EPS
0
3
WLS0
0
1
0
1
PEN
0
2
STB
0
1
WLS1
0
0
Reset
Required
WLS0
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
Character Length
5 (Default)
6
7
8
Register (LCR)
Link Control
Offset 03h
All Banks,
146
Bit 5 - Stick Parity (STKP)
Bit 6 - Set Break (SBRK)
Bit 7 - Bank Select Enable (BKSE)
1 - If parity is enabled, an even number of logic 1s are
When Parity is enabled (PEN is 1), this bit, together with
bit 4 (EPS), controls the parity bit as show in Table 7-8.
This bit enables or disables a break. During the break,
the transmitter can be used as a character timer to ac-
curately establish the break duration.
This bit acts only on the transmitter front-end and has no
effect on the rest of the transmitter logic.
When set to 1 the following occurs:
— If a UART mode is selected, the SOUT pin is forced
— If SIR mode is selected, pulses are issued continu-
— If Sharp-IR mode is selected and internal modula-
— If Sharp-IR mode is selected and internal modula-
To avoid transmission of erroneous characters as a re-
sult of the break, use the following procedure to set
SBRK:
1. Wait for the transmitter to be empty. (TXEMP = 1).
2. Set SBRK to 1.
3. Wait for the transmitter to be empty, and clear SBRK
0 - This register functions as the Link Control Register
1 - This register functions as the Bank Select Register
PEN
0
1
1
1
1
TABLE 7-8. Bit Settings for Parity Control
transmitted or checked.
to a logic 0 state.
ously on the IRTX pin.
tion is enabled, pulses are issued continuously on
the IRTX pin.
tion is disabled, the IRTX pin is forced to a logic 1
state.
when normal transmission must be restored.
(LCR).
(BSR).
EPS
x
0
1
0
1
STKP
x
0
0
1
1
Selected Parity Bit
Logic 1
Logic 0
None
Even
Odd