PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 214

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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DSR
DTR
EAR
ECP
ECR
EDR
EIR
Extended UART Operation Mode
EPP
EXCR1 and EXCR2
FCR
FDC
FDD
FER1 and FER2
FIFO
GPIO
Data rate Select Register of the Floppy Disk Con-
troller (FDC) for write operations (logical device 3,
offset 4h) and the Data Status Register in Extend-
ed Capabilities Port (ECP) modes (logical device 4,
offset 001h).
Data Register of the parallel port in SPP or EPP
modes. (Logical device 4, offset 00h.)
Extended Auxiliary Register of the parallel port in
Extended Capabilities Port (ECP) modes. (Logical
device 4, offset 405h.)
Extended Capabilities Port.
Extended Control Register for the parallel port in
Extended Capabilities Port (ECP) modes. (Logical
device 4, offset 402h.)
Extended Data Register for the parallel port in ex-
tended Capabilities Port (ECP) modes. (Logical de-
vice 4, offset 404h.).
Extended Index Register of the parallel port Ex-
tended Capabilities Port (ECP) modes (logical de-
vice 4, offset 403h) and Event Identification
Register for UART1 (logical device 6, offset 01h, di-
visor latch registers not accessible, bit 7 of LCR =
0) and for UART2 for read cycles (logical device 5,
bank 0, offset 02h).
This UART operation mode supports standard
16450 and 16550A UART operations plus addition-
al interrupts and DMA features. It does not include
infrared or Consumer Remote Control modes.
Enhanced Parallel Port.
Extended Control Registers 1 and 2 for UART2.
(Logical device 5, bank 2, offsets 02h and 04h, re-
spectively.)
The FIFO Control Register for UART1 (logical de-
vice 6, offset 02h) and for UART2 for write cycles
(logical device 5, bank 0, offset 02h).
Floppy Disk Controller.
Floppy Disk Drive.
Function Enable Registers of the Power Manage-
ment device (Logical device 8, offsets 00h and 01h,
respectively.).
Data register (FIFO queue) of the Floppy Disk Con-
troller (FDC). (Logical device 3, offset 05h.)
General Purpose I/O - I/O pins available for general
use.
Glossary
214
IER
IIR
Index
IR
IRCFG1, IRCFG3 and IRCFG4
IRCR1, IRCR2 and IRCR3
IrDA
IrDA-2 mode
IRQ
IRRXDC
IRTXMC
ISA
LCR
Legacy
Legacy Mode
LFSR
LSB
LSR
The Interrupt Enable Register for UART1 (logical
device 6, offset 01h, divisor latch registers not ac-
cessible, bit 7 of LCR = 0) and for UART2 (logical
device 5, bank 0, offset 01h).
The Interrupt Identification Register for UART1.
(Logical device 6, offset 02h.)
The Index register is a pointer that is used to ad-
dress other registers.
InfraRed.
Infrared module Configuration registers for UART2.
(Logical device 5, bank 7, offsets 04h, 06h and
07h, respectively.)
Infrared Module Control Registers 1, 2 and 3 for
UART2. (Logical device 5. IRCR1 is in bank 4, off-
set 02h; IRCR2 is in bank 5, offset 04h; IRCR3 is in
bank 6, offset 00h.)
Infrared Data Association.
In this mode, the part provides the Infrared Data
Association standard compliant interface.
Interrupt Request.
Infrared Receiver Demodulator Control register for
UART2. (Logical device 5, bank 7, offset 00h.)
Infrared Transmitter Modulator Control register for
UART2. (Logical device 5, bank 7, offset 01h.)
Industry Standard Architecture for the PC bus.
Line Control Register for UART1 (logical device 6,
offset 03h) and for UART2 when enabled, i.e.,
when bit 7 of this register is 0 (logical device 5, all
banks, offset 03h).
Usually refers to older devices or systems that are
not Plug and Play compatible.
In this mode, the interrupts and the base addresses
of the FDC, UARTs, KBC, RTC and the parallel
port of the part are configured as in earlier Su-
perI/O chips.
The Linear Feedback Shift Register. In Plug and
Play mode, this register is used to prepare the chip
for operation in Plug and Play (PnP) mode.
Least Significant Byte or Bit.
Line Status Register for UART1 (logical device 6,
offset 05h) and for UART2 in Non-Extended modes
only (logical device 5, bank 0, offset 05h).