PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 215

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

MCR
MSB
MSR
Non-Extended UART Operation Modes
NVM
P_BGDH and P_BGDL
PIO
P_MDR
Plug and Play
PM
PMC1, PMC2 and PMC3
PnP
PnP Mode
PP Confg0
Precompensation
RBR
Modem Control Register for UART1 (logical device
6, offset 04h) and for UART2 (logical device 5,
bank 0, offset 04h).
Most Significant Byte or Bit.
Main Status Register of the Floppy Disk Controller
(FDC) (logical device 3, offset 4h) and Modem Sta-
tus Register for UART1 for read operations (logical
device 6, offset 06h) and for UART2 (logical device
5, bank 0, offset 06h).
These UART operation modes support only UART
operations that are standard for 15450 or 16550A
devices.
Non-volatile memory.
Pipeline Baud rate Generator Divisor buffer (High
and Low bytes) for UARTs. (Logical devices 5 and
6, bank 5, offsets 01h and 00h, respectively.)
Programmable Input/Output.
Pipeline Mode Register for UARTs. (Logical devic-
es 5 and 6, bank 5, offset 02h.)
A design philosophy and a set of specifications that
describe hardware and software changes to the PC
and its peripherals that automatically identify and
arbitrate resource requirements among all devices
and buses on the system. Plug and Play is some-
times abbreviated as PnP.
Power Management.
Power Management Control registers of logical de-
vice 8 at offsets 02h, 03h and 04h, respectively.
Sometimes used to indicate Plug and Play.
In this mode, the interrupts, the DMA channels and
the base address of the FDC, UARTs, KBC, RTC,
GPIO, APC and the Parallel Port of the part are ful-
ly Plug and Play.
Internal configuration register of the Parallel Port in
Extended Capabilities Port (ECP) modes. (Logical
device 4, second level offset 05h.)
Also called write precompensation, is a way of pre-
conditioning the
the effects of bit shift on the data as it is written to
the disk surface.
Receiver Buffer Register for UART1, read opera-
tions only (logical device 6, offset 00h, divisor latch
registers not accessible, bit 7 of LCR = 0).
WDATA
output signal to adjust for
Glossary
215
RCCFG
RLC
RLE
RLR
RSR
RTC
RXDR
RXFLV
SCR
SH_FCR
SH_LCR
Sharp IR
Sharp IR Mode
SIO
SIR
SIR_PW
SPP
SRA and SRB
ST0, ST1, ST2 and ST3
Consumer Remote Control Configuration register
for UART2. (Logical device 5, bank 7, offset 02h.)
Run Length Count byte for parallel ports.
Run Length Expander for parallel ports.
RAM Lock Register for Advanced Power Control
(APC). (Logical device 2, offset 47h.)
Internal Receiver Shift Register for UART1.
Real-Time Clock.
Receiver Data Register for read cycles for UART2.
(Logical device 5, bank 0, offset 00h.)
Reception FIFO Level for UART2. (Logical device
5, bank 2, offset 07h.)
Scratch Register for UART1 (logical device 6, off-
set 07h) and for UART2 in UART operation mode
(logical device 5, bank 0, offset 07h).
Shadow of the FIFO Control Register (FCR) for
UART2 for read operations. (Logical device 5, bank
3, offset 02h.)
Shadow of the Line Control Register (LCR) for
UART2 for read operations. (Logical device 5, bank
3, offset 01h.)
Sharp Infrared.
In this mode, the part supports a Sharp Infrared in-
terface.
SuperI/O, sometimes used to refer to a chip that
has
PC87307/PC97307 VUL device.
Serial Infrared.
SIR Pulse Width control for UART2. (Logical device
5, bank 6, offset 02h.)
The Standard Parallel Port configuration of the Par-
allel Port device (Logical device 4) supports the
Compatible SPP mode and the Extended PP
mode.
Status Registers A and B of the Floppy Disk Con-
troller (FDC). (Logical device 3, offsets 0h and 1h,
respectively.)
Status registers 0, 1, 2 and 3 of the Floppy Disk
Controller (FDC).
SuperI/O
capabilities,
e.g.,
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the