PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 69

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

5.2.5
Write precompensation enables the WDATA output signal
to adjust for the effects of bit shift on the data as it is written
to the disk surface.
Bit shift is caused by the magnetic interaction of data bits as
they are written to the disk surface. It shifts these data bits
away from their nominal position in the serial MFM data pat-
tern. Bit shift makes it much harder for a data separator to
read data and can cause soft read errors.
Write precompensation predicts where bit shift could occur
within a data pattern. It then shifts the individual data bits
early, late, or not at all so that when they are written to the
disk, the shifted data bits are back in their nominal position.
The FDC supports software programmable write precom-
pensation. Upon power up, the default write precompensa-
tion values shown in Table 5-8 on page 76, are used. In
addition, the default starting track number for write precom-
pensation is track zero
You can use the DSR to change the write precompensation
using any of the values in Table 5-7 on page 76. Also, the
CONFIGURE command can change the starting track num-
ber for write precompensation.
5.2.6
The FDC of the part supports two low-power modes, man-
ual and automatic.
In low-power mode, the micro-code is driven from the clock.
Therefore, it is disabled while the clock is off. Upon entering
the power-down state, bit 7, the RQM (Request For Master)
bit, in the Main Status Register (MSR) of the FDC is cleared
to 0.
For details about entering and exiting low-power mode by
setting bit 6 of the Data rate Select Register (DSR) or by ex-
ecuting the LOW PWR option of the FDC MODE command,
see “Recovery from Low-Power Mode” later in this section,
the “Data Rate Select Register (DSR), Offset 04h,
Write Operations” on page 75 and “The MODE Command”
on page 92.
The DSR, Digital Output Register (DOR), and the Configu-
ration Control Register (CCR) are unaffected and remain
active in power-down mode. Therefore, you should make
sure that the motor and drive select signals are turned off.
If the power to an external clock driving the part will be in-
dependently removed while the FDC is in power-down
mode, it must not be done until 2 msec after the LOW PWR
option of the FDC MODE command is issued.
Manual Low-Power Mode
Manual low power is enabled by writing a 1 to bit 6 of the
DSR. The chip will power down immediately. This bit will be
cleared to 0 after power up.
Manual low power can also be triggered by the MODE com-
mand. Manual low power mode functions as a logical OR
function between the DSR low power bit and the LOW PWR
option of the MODE command.
Automatic Low-Power Mode
Automatic low-power mode switches the controller to low
power 500 msec (at the 500 Kbps MFM data rate) after it
has entered the Idle state. Once automatic low-power mode
is set, it does not have to be set again, and the controller au-
tomatically goes into low-power mode after entering the Idle
state.
Write Precompensation
FDC Low-Power Mode Logic
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
69
Automatic low-power mode can only be set with the LOW
PWR option of the MODE command.
Recovery from Low-Power Mode
There are two ways the FDC section can recover from the
power-down state.
Power up is triggered by a software reset via the DOR or
DSR. Since a software reset requires initialization of the
controller, this method might be undesirable.
Power up is also triggered by a read or write to either the
Data Register (FIFO) or Main Status Register (MSR). This
is the preferred way to power up since all internal register
values are retained. It may take a few milliseconds for the
clock to stabilize, and the microprocessor will be prevented
from issuing commands during this time through the normal
MSR protocol. That means that bit 7, the Request for Mas-
ter (RQM) bit, in the MSR will be a 0 until the clock has sta-
bilized. When the controller has completely stabilized after
power up, the RQM bit in the MSR is set to 1 and the con-
troller can continue where it left off.
5.2.7
The FDC can be reset by hardware or software.
A hardware reset consists of pulsing the Master Reset (MR)
input signal. A hardware reset sets all of the user address-
able registers and internal registers to their default values.
The SPECIFY command values are unaffected by reset, so
they must be initialized again.
The major default conditions affected by reset are:
A software reset can be triggered by bit 2 of the Digital Out-
put Register (DOR) or bit 7 of the Data rate Select Register
(DSR). Bit 7 of DSR clears itself, while bit 2 of DOR does
not clear itself.
If the LOCK bit in the LOCK command was set to 1 before
the software reset, the FIFO, THRESH, and PRETRK pa-
rameters in the CONFIGURE command will be retained. In
addition, the FWR, FRD, and BST parameters in the MODE
command will be retained if LOCK is set to 1. This function
eliminates the need for total initialization of the controller af-
ter a software reset.
After a hardware (assuming the FDC is enabled in the FER)
or software reset, the Main Status Register (MSR) is imme-
diately available for read access by the microprocessor. It
will return a 00h value until all the internal registers have
been updated and the data separator is stabilized.
When the controller is ready to receive a command byte, the
MSR returns a value of 80h (Request for Master (RQM, bit
7) bit is set). The MSR is guaranteed to return the 80h value
within 250 sec after a hardware or software reset.
All other user addressable registers other than the Main
Status Register (MSR) and Data Register (FIFO) can be ac-
cessed at any time, even during software reset.
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FIFO disabled
DMA disabled
Implied seeks disabled
Drive polling enabled
Reset
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