PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 105

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

First Command Phase Byte, Bit 6 - Write Track Number
(WNR)
Second Command Phase Byte
Bits 1,0 - Logical Drive Select (DS1,0)
Bit 2 - Most Significant Byte (MSB)
Execution Phase
Internal register is read or written.
Result Phase
This byte is one byte of the track number that was read or
written, depending on the value of WNR in the first com-
mand byte.
TABLE 5-23. Defining Bytes to Read or Write Using
MSB
7
0 - Read the existing track number.
1 - Change the track number by writing a new value to
These bits indicate which logical drive is active. See
“Bits 1,0 - Logical Drive Select (DS1,0)” on page 90.
00 - Drive 0 is selected.
01 - Drive 1 is selected.
10 - If four drives are supported, or drives 2 and 0 are
11 - If four drives are supported, drive 3 is selected.
This bit, together with bits 1,0, determines the byte to
read or write. See also Table 5-23.
0 - Least significant byte of the track number.
1 - Most significant byte of the track number.
2
0
1
0
1
0
1
0
1
The result phase byte already contains the track
number, and the third byte in the command phase
is a dummy byte.
the result phase byte.
exchanged, drive 2 is selected.
6
Byte of Present Track Number(PTR)
DS1
1
0
0
0
0
1
1
1
1
5
DS0
SET TRACK
0
0
0
1
1
0
0
1
1
4
Byte to Read or Write
3
Drive 0 (MSB)
Drive 1 (MSB)
Drive 2 (MSB)
Drive 3 (MSB)
Drive 0 (LSB)
Drive 1 (LSB)
Drive 2 (LSB)
Drive 3 (LSB)
2
1
0
105
5.7.21 The SPECIFY Command
The SPECIFY command sets initial values for the following
time periods:
The FDC uses the Digital Output Register (DOR) to enable
the drive and motor select signals. See also, “Digital Output
Register (DOR), Offset 02h” on page 71.
The delays may be used to support the PD765, i.e., to in-
sert delays from selection of a drive motor until a read or
write operation starts, and from termination of a command
until the drive motor is no longer selected, respectively.
The parameters used by this command are undefined after
power up, and are unaffected by any reset. Therefore, soft-
ware should always issue a SPECIFY command as part of
an initialization routine to initialize these parameters.
Termination of this command does not generate an inter-
rupt.
Command Phase
Second Command Phase Byte
Bits 3-0 - Delay After Processing Factor
Bits 7-4 - STEP Time Interval Value (SRT)
•
•
•
7
0
Step Rate Time (SRT)
The delay before command processing starts, formerly
called Motor On Time (MNT)
The delay after command processing terminates, for-
merly called Motor Off Time (MFT)
The interval step rate time.
These bits specify a factor that is multiplied by a con-
stant to determine the delay after command processing
ends, i.e., from termination of a command until the drive
motor is no longer selected.
The value of the Motor Timer Values (TMR) bit (bit 7) of
the second command phase byte in the MODE com-
mand determines which group of constants and delay
ranges to use. See “Bit 7 - Motor Timer Values (TMR)”
on page 93.
The specific constant that will be multiplied by this factor
to determine the actual delay after processing for each
data transfer rate is shown in Table 5-24.
Use the smallest possible value for this factor, except 0,
i.e., 1. If this factor is 0, the value16 is used.
These bits specify a value that is used to calculate the
time interval between successive STEP signal pulses
during a SEEK, IMPLIED SEEK, RECALIBRATE, or
RELATIVE SEEK command.
Table 5-26 shows how this value is used to calculate the
actual time interval.
6
0
Delay Before Processing
5
0
.
4
0
3
0
Delay After Processing
2
0
www.national.com
1
1
DMA
0
1