PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 18

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
GPIO20
GPIO21
GPIO22
GPIO23
GPIO27-24
HDSEL
ID0
ID1
ID2
ID3
INDEX
INIT
IOCHRDY
IRQ1
IRQ5-3
IRQ12-6
IRQ15,14
IRRX2,1
IRSL0
IRSL1
IRSL2
Signal/Pin
Name
157
77, 158
159
160
76-73
92
79
78 or 157
158
70
97
117
32
36
39-37
47-41
49,48
79, 80
79 or 158
78 or 157
77 or 158
79, 78, 77
158, 157
Number
Pin
Parallel Port
Purpose
ISA-Bus
ISA-Bus
General
Module
UART2
UART2
UART2
(SIR)
(SIR)
FDC
FDC
Signal/Pin Connection and Description
Group 10
Group 16
Group 13
Group 22
Group 15
Group 17
Group 10
Group #
Group 1
Group 1
Group 1
I/O and
Output
Output
Output
Input
Input
Input
I/O
I/O
I/O
General Purpose I/O Signals 27-20 – General purpose I/O port 2
signals.
GPIO27-24 are multiplexed with XD5-2, respectively.
GPIO23 is multiplexed with RING.
GPIO22 is multiplexed with POR.
GPIO21 is multiplexed on pin 158 with IRSL2, IRSL0 and on pin 77
with IRSL2, SELCS and XD6. See “SuperI/O Configuration 2
Register, Index 22h” on page 35.
GPIO20 is multiplexed with IRSL1.
Head Select – This output signal determines which side of the FDD
is accessed. Active low selects side 1, inactive selects side 0.
Identification – These ID signals identify the infrared transceiver for
Plug and Play support. These pins are read after reset.
ID0 is multiplexed on pin 79 with IRRX2 and IRSL0.
ID1 is multiplexed on pin 78 with IRSL1 and XD7, or on pin 157 with
GPIO20 and IRSL1.
ID2 is multiplexed on pin 158 with GPIO21, IRSL2 and IRSL0.
ID3 is multiplexed on pin 70 with XDRD.
See Table 1-2 on page 23 for more information.
Index – This input signal indicates the beginning of an FDD track.
Initialize – When this signal is active low, it causes the printer to be
initialized. This signal is in TRI-STATE after a 1 is loaded into the
corresponding control register bit.
An external 4.7 K
I/O Channel Ready – This is the I/O channel ready open drain
output signal. When IOCHRDY is driven low, the EPP extends the
host cycle.
Interrupt Requests 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14 and 15 – IRQ
polarity and push-pull or open-drain output selection is software
configurable by the logical device mapped to the IRQ line.
Keyboard Controller (KBC) or Mouse interrupts can be configured by
the Interrupt Request Type Select 0 register (index 71h) as either
edge or level.
The parallel port interrupt is either edge or level, according to the
operation mode (default edge, configured by the SuperI/O Parallel
Port Configuration register at index F0h).
Infrared Reception 1 and 2 – Infrared serial input data.
IRRX2 is multiplexed with IRSL0 and ID0. See Table 1-2 on page 23
for more information.
Infrared Control Signals 0, 1 and 2 – These signals control the
Infrared analog front end. The pins on which these signals are driven
is determined by the SuperI/O Configuration 2 register (index 22h).
See Section 2.4.4 on page 35. IRSL0 or ID0/IRRX2 on pin 79 is
determined by UART2 bit 5 of the IRCFG4 register (See page 165).
IRSL0 is multiplexed on pin 79 with IRRX2 and ID0, or on pin 158
with GPIO21, IRSL2 and ID2.
IRSL1 is multiplexed on pin 78 with XD7 and ID1, or on pin 157 with
GPIO20 and ID1.
IRSL2 is multiplexed on pin 77 with XD6, SELCS and GPIO21, or on
pin 158 with GPIO21, IRSL0 and ID2.
18
pull-up resistor should be employed.
Function