PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 39

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

2.10 PROGRAMMABLE CHIP SELECT
The chip select configuration registers are accessed using
two index levels. The first index level accesses the Pro-
grammable Chip Select Index register at 23h. See Section
2.4.5 on page 35. The second index level accesses a spe-
cific chip select configuration register as shown in Table
2-22.
See also, “Programmable Chip Select Output Signals” on
page 171 and the description of each signal in Table 1-1 on
page 15.
2.10.1 CS0 Base Address MSB, Second Level
This read/write register is reset by hardware to 00h. Same
as Plug and Play ISA base address register at index 60h.
See Table 2-7 on page 28.
2.10.2 CS0 Base Address LSB Register, Second Level
This read/write register is reset by hardware to 00h. It is the
same as the Plug and Play ISA base address register at in-
dex 61h. See Table 2-7 on page 28.
2.10.3 CS0 Configuration Register, Second Level
This read/write register is reset by hardware to 00h. It con-
trols activation of the CS0 signal upon an address match,
when AEN is inactive (low) and the non-masked address
pins match the corresponding base address bits.
0Bh-0Fh
10h-FFh
Second
Index
Level
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
CONFIGURATION REGISTERS
TABLE 2-22. The Programmable Chip Select
Index 00h
Index 01h
Index 02h
CS0 Base Address MSB Register R/W 00h
CS1 Base Address MSB Register R/W 00h
CS2 Base Address MSB Register R/W 00h
CS0 Base Address LSB Register R/W 00h
CS1 Base Address LSB Register R/W 00h
CS2 Base Address LSB Register R/W 00h
CS0 Configuration Register
CS1 Configuration Register
CS2 Configuration Register
Configuration Registers
Register Name
Not Accessible
Reserved
Reserved
Reserved
Type Reset
R/W 00h
R/W 00h
R/W 00h
-
-
-
-
Configuration
-
-
-
-
39
Bit 0 - Mask Address Pin A0
Bit 1 - Mask Address Pin A1
Bit 2 - Mask Address Pin A2
Bit 3 - Mask Address Pin A3
Bit 4 - Assert Chip Select Signal on Write
Bit 5 - Assert Chip Select Signal on Read
Bit 6 - Unaffected by RD/WR
Bit 7 - Mask Address Pins A11-A0
2.10.4 Reserved, Second Level Index 03h
Attempts to access this register produce undefined results.
0
7
FIGURE 2-14. CS0 Configuration Register Bitmap
0 - A0 is decoded.
1 - A0 is not decoded; it is ignored.
0 - A1 is decoded.
1 - A1 is not decoded (ignored).
0 - A2 is decoded.
1 - A2 is not decoded; it is ignored.
0 - A3 is decoded.
1 - A3 is not decoded; it is ignored.
0 - Chip select not asserted on address match and
1 - Chip select asserted on address match and when
0 - Chip select not asserted on address match and
1 - Chip select asserted on address match and when
Bits 5 and 4 are ignored when this bit is set.
0 - Chip select asserted on address match, qualified by
1 - Chip select asserted on address match, regardless
0 - A11-A0 are decoded.
1 - A11-A0 are not decoded; they are ignored.
0
Mask Address Pins A11-A0
6
when WR is active (low).
WR is active (low).
when RD is active (low).
RD is active (low).
RD or WR pin state and contents of bits 5 and 4.
of RD or WR pin state and regardless of contents
of bits 5 and 4.
Unaffected by RD/WR
0
5
Assert Chip Select Signal on Read
0
4
Assert Chip Select Signal on Write
0
3
Mask Address Pin A3
0
2
Mask Address Pin A2
0
1
Mask Address Pin A1
0
0
Reset
Required
Mask Address Pin A0
CS0 Configuration
Second Level
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Index 02h
Register,