IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 97

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2
Programming Information
IDT82V3380A
Address: 25H
Type: Read / Write
Default Value: X0000000
6 - 0
Bit
7
7
-
PRE_DIVN_VALUE[14:8]
PRE_DIVN_VAL
Name
UE14
-
6
PRE_DIVN_VAL
Reserved.
If the value in the PRE_DIVN_VALUE[14:0] bits is plus 1, the division factor for an input clock will be gotten. The input
clock is selected by the PRE_DIV_CH_VALUE[3:0] bits (b3~0, 23H).
A value from ‘1’ to ‘4BEF’ (Hex) can be written into, corresponding to a division factor from 2 to 19440. The others are
reserved. So the DivN Divider only supports an input clock whose frequency is less than or equal to (≤) 155.52 MHz.
The division factor setting should observe the following order:
1. Write the lower eight bits of the division factor to the PRE_DIVN_VALUE[7:0] bits;
2. Write the higher eight bits of the division factor to the PRE_DIVN_VALUE[14:8] bits.
UE13
5
PRE_DIVN_VAL
UE12
4
97
PRE_DIVN_VAL
UE11
3
Description
PRE_DIVN_VAL
UE10
SYNCHRONOUS ETHERNET WAN PLL™
2
PRE_DIVN_VAL
UE9
1
PRE_DIVN_VAL
May 16, 2011
UE8
0