IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 66

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

Table 46: Register List and Map (Continued)
Programming Information
IDT82V3380A
Address
(Hex)
4A
4B
4C
4D
4E
5A
48
49
4F
50
51
52
53
54
55
56
57
58
59
IN11_IN12_STS - Input Clock 11 & 12
Status
IN13_IN14_STS - Input Clock 13 & 14
Status
INPUT_VALID1_STS - Input Clocks
Validity 1
INPUT_VALID2_STS - Input Clocks
Validity 2
REMOTE_INPUT_VALID1_CNFG
Input Clocks Validity Configuration 1
REMOTE_INPUT_VALID2_CNFG
Input Clocks Validity Configuration 2
PRIORITY_TABLE1_STS - Priority
Status 1 *
PRIORITY_TABLE2_STS - Priority
Status 2 *
T0_INPUT_SEL_CNFG - T0 Selected
Input Clock Configuration
T4_INPUT_SEL_CNFG - T4 Selected
Input Clock Configuration
OPERATING_STS - DPLL Operating
Status
T0_OPERATING_MODE_CNFG - T0
DPLL Operating Mode Configuration
T4_OPERATING_MODE_CNFG - T4
DPLL Operating Mode Configuration
T0_DPLL_APLL_PATH_CNFG - T0
DPLL & APLL Path Configuration
T0_DPLL_START_BW_DAMPING_C
NFG - T0 DPLL Start Bandwidth &
Damping Factor Configuration
T0_DPLL_ACQ_BW_DAMPING_CNF
G - T0 DPLL Acquisition Bandwidth &
Damping Factor Configuration
T0_DPLL_LOCKED_BW_DAMPING_
CNFG - T0 DPLL Locked Bandwidth &
Damping Factor Configuration
T0_BW_OVERSHOOT_CNFG - T0
DPLL Bandwidth Overshoot Configu-
ration
PHASE_LOSS_COARSE_LIMIT_CNF
G - Phase Loss Coarse Detector Limit
Configuration *
Register Name
-
-
PH_LOS_L
IN8_VALID IN7_VALID IN6_VALID IN5_VALID IN4_VALID IN3_VALID IN2_VALID IN1_VALID
AUTO_BW
COARSE_
EX_SYNC
_ALARM_
T0_DPLL_LOCKED_DAMPING[2:0]
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
T0_DPLL_START_DAMPING[2:0]
IMT_EN
T0_DPLL_ACQ_DAMPING[2:0]
_SEL
MON
Bit 7
HIGHEST_PRIORITY_VALIDATED[3:0]
-
-
-
-
-
-
-
-
T0 / T4 DPLL State Machine Control Registers
T0 / T4 DPLL & APLL Configuration Registers
T0 / T4 DPLL Input Clock Selection Registers
T4_LOCK_
IN12_FRE
Q_HARD_
IN14_FRE
Q_HARD_
T4_DPLL_
WIDE_EN
ALARM
ALARM
T0_APLL_PATH[3:0]
LOCK
Bit 6
T0
-
-
-
-
-
-
ACTIVITY_
ACTIVITY_
T0_FOR_T
MULTI_PH
IN12_NO_
IN14_NO_
IN14_VALI
T0_DPLL_
SOFT_FR
EQ_ALAR
ALARM
ALARM
_APP
Bit 5
66
M
D
4
-
-
-
-
T4_TEST_
MULTI_PH
IN14_PHA
IN13_VALI
T4_DPLL_
_8K_4K_2
IN12_PH_
LOCK_AL
SE_LOCK
SOFT_FR
EQ_ALRA
_ALARM
T0_PH
K_EN
Bit 4
ARM
D
M
-
-
-
-
IN[8:1]
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0
T0_ETH_OBSAI_16E1_
IN12_VALI
T0_DPLL_
T0_LIMT
LOCK
Bit 3
T0_DPLL_LOCKED_BW[4:0]
16T1_SEL[1:0]
D
T0_DPLL_START_BW[4:0]
-
-
-
-
CURRENTLY_SELECTED_INPUT[3:0]
T0_DPLL_ACQ_BW[4:0]
IN[14:9]
PH_LOS_COARSE_LIMT[3:0]
SYNCHRONOUS ETHERNET WAN PLL™
Q_HARD_
IN13_FRE
Q_HARD_
IN11_VALI
T0_DPLL_OPERATING_MODE[2:0]
IN11_FRE
ALARM
ALARM
T0_INPUT_SEL[3:0]
T4_INPUT_SEL[3:0]
Bit 2
T0_OPERATING_MODE[2:0]
T4_OPERATING_MODE[2:0]
D
-
]
ACTIVITY_
ACTIVITY_
IN13_NO_
IN10_VALI
IN11_NO_
T0_12E1_24T1_E3_T3
ALARM
ALARM
Bit 1
D
-
_SEL[1:0]
IN11_PH_L
IN9_VALID
IN13_PHA
OCK_ALA
SE_LOCK
_ALARM
Bit 0
RM
-
May 16, 2011
Reference
P 120
P 120
P 121
P 121
P 122
P 123
P 124
P 124
P 125
P 126
P 127
P 128
P 129
P 130
P 117
P 118
P 119
P 119
P 119
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