IDT82V3380A Integrated Device Technology, IDT82V3380A Datasheet
IDT82V3380A
Related parts for IDT82V3380A
IDT82V3380A Summary of contents
Page 1
... SYNCHRONOUS ETHERNET IDT WAN PLL™ IDT82V3380A Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Version 3 September 30, 2010 6024 Silver Creek Valley Road, San Jose, CA 95138 Printed in U.S.A. © 2010 Integrated Device Technology, Inc. ...
Page 2
... Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos- sible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use ...
Page 3
FEATURES .............................................................................................................................................................................. 9 HIGHLIGHTS.................................................................................................................................................................................................... 9 MAIN FEATURES ............................................................................................................................................................................................ 9 OTHER FEATURES ......................................................................................................................................................................................... 9 APPLICATIONS....................................................................................................................................................................... 9 DESCRIPTION....................................................................................................................................................................... 10 FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11 1 PIN ASSIGNMENT ........................................................................................................................................................... 12 2 PIN DESCRIPTION .......................................................................................................................................................... 13 3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 19 3.1 RESET ........................................................................................................................................................................................................... ...
Page 4
... IDT82V3380A 3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 34 3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 34 3.10.1.5 Holdover Mode ................................................................................................................................................................. 34 3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 35 3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 35 3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 35 3.10.1.5.4 Manual ........................................................................................................................................................... 35 3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 35 3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 35 3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 35 3.10.2.1 Free-Run Mode ................................................................................................................................................................ 35 3.10.2.2 Locked Mode .................................................................................................................................................................... 35 3.10.2.3 Holdover Mode ................................................................................................................................................................. 35 3. DPLL OUTPUT ................................................................................................................................................................................. 37 3.11.1 PFD Output Limit ............................................................................................................................................................................ 37 3.11.2 Frequency Offset Limit .................................................................................................................................................................. 37 3 ...
Page 5
... IDT82V3380A 8.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 152 8.3 HEATSINK EVALUATION .......................................................................................................................................................................... 152 8.4 TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 153 9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 154 9.1 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 154 9.2 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 154 9.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 155 9.3.1 AMI Input / Output Port ................................................................................................................................................................ 155 9.3.1.1 Structure ......................................................................................................................................................................... 155 9.3.1.2 I/O Level ......................................................................................................................................................................... 155 9.3.1.3 Over-Voltage Protection ................................................................................................................................................. 157 9.3.2 CMOS Input / Output Port ............................................................................................................................................................ 157 9 ...
Page 6
Table 1: Pin Description ............................................................................................................................................................................................. 13 Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 19 Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 20 Table 4: Pre-Divider Function .................................................................................................................................................................................... 22 Table 5: Related Bit / Register ...
Page 7
... IDT82V3380A Table 49: Absolute Maximum Rating ......................................................................................................................................................................... 154 Table 50: Recommended Operation Conditions ........................................................................................................................................................ 154 Table 51: AMI Input / Output Port Electrical Characteristics ...................................................................................................................................... 156 Table 52: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 157 Table 53: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 157 Table 54: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 157 Table 55: CMOS Output Port Electrical Characteristics ...
Page 8
... Figure 13 Late Frame Sync 2K/8K Pulse Input Signal Timing ............................................................................................................................ 45 Figure 14. On Target Frame Sync 2K/8K Pulse Input Signal Timing .......................................................................................................................... 45 Figure 15. Physical Connection Between Two Devices .............................................................................................................................................. 47 Figure 16. IDT82V3380A Power Decoupling Scheme ................................................................................................................................................. 49 Figure 17. Typical Application ...................................................................................................................................................................................... 50 Figure 18. EPROM Access Timing Diagram ............................................................................................................................................................... 52 Figure 19. Multiplexed Read Timing Diagram ............................................................................................................................................................. 53 Figure 20 ...
Page 9
... Gigabit and Terabit IP switches / routers • IP and ATM core switches and access equipments • Cellular and WLL base-station node clocks • Broadband and multi-service access equipments • Any other telecom equipments that need synchronous equipment system timing 9 IDT82V3380A September 30, 2010 DSC-7236/1 ...
Page 10
... IDT82V3380A DESCRIPTION The IDT82V3380A is an integrated, single-chip solution for the Syn- chronous Equipment Timing Source for Stratum 2, 3E, 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, Router and Access Network appli- cations. The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing ...
Page 11
... IDT82V3380A FUNCTIONAL BLOCK DIAGRAM Functional Block Diagram Figure 1. Functional Block Diagram 11 SYNCHRONOUS ETHERNET IDT WAN PLL™ September 30, 2010 ...
Page 12
... VDDD3 14 DGND3 15 DGND2 VDDD2 16 17 IC3 18 FF_SRCSW 19 VDDA2 20 AGND2 TDO 21 22 IC4 TDI 23 IN1 24 IN2 25 Pin Assignment IDT82V3380A Figure 2. Pin Assignment (Top View) 12 SYNCHRONOUS ETHERNET IDT WAN PLL™ 75 RDY 74 RST 73 ALE/SCLK A0/SDI 68 A1/CLKE ...
Page 13
... IDT82V3380A 2 PIN DESCRIPTION Table 1: Pin Description Name Pin No. I/O OSCI FF_SRCSW 18 pull-down I MS/SL 99 pull-up I SONET/SDH 100 pull-down I 74 RST pull-up I EX_SYNC1 45 pull-down IN1 24 I IN2 IN3 46 pull-down I IN4 47 pull-down IN5_POS 40 I IN5_NEG 41 Pin Description Type Global Control Signal OSCI: Crystal Oscillator Master Clock CMOS A nominal 12 ...
Page 14
... IDT82V3380A Table 1: Pin Description (Continued) Name Pin No. I/O IN6_POS 42 I IN6_NEG 43 I IN7 48 pull-down I IN8 51 pull-down I IN9 52 pull-down I IN10 53 pull-down I IN11 54 pull-down I IN12 55 pull-down I IN13 56 pull-down I IN14 57 pull-down FRSYNC_8K 30 O MFRSYNC_2K 31 O OUT1 88 O OUT2 89 O Pin Description Type IN6_POS / IN6_NEG: Positive / Negative Input Clock 6 ...
Page 15
... IDT82V3380A Table 1: Pin Description (Continued) Name Pin No. I/O OUT3 90 O OUT4 93 O OUT5 94 O OUT6_POS 34 O OUT6_NEG 35 OUT7_POS 36 O OUT7_NEG 37 OUT8_POS 28 O OUT8_NEG 27 OUT9 I/O pull-up INT_REQ 8 O MPU_MODE0 60 I MPU_MODE1 59 pull-down MPU_MODE2 58 Pin Description Type OUT3: Output Clock Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz CMOS 10 MHz, 20 MHz, 25 MHz, E3, T3, 6 ...
Page 16
... IDT82V3380A Table 1: Pin Description (Continued) Name Pin No. I SDI CLKE I pull-down AD0 / SDO 83 AD1 82 AD2 81 AD3 80 I/O pull-down AD4 79 AD5 78 AD6 77 AD7 pull- pull-up I ALE / SCLK 73 pull-down Pin Description Type A[6:0]: Address Bus In EPROM mode, these pins are outputs. They are the address bus of the EPROM interface. ...
Page 17
... IDT82V3380A Table 1: Pin Description (Continued) Name Pin No. I/O RDY TRST pull-down I TMS 7 pull-up I TCK 9 pull-down I TDI 23 pull-up TDO 21 O VDDD1 12 VDDD2 16 VDDD3 13 VDDD4 50 Power VDDD5 61 VDDD6 85 VDDD7 86 VDDA1 6 VDDA2 19 Power VDDA3 91 VDD_AMI 26 Power VDD_DIFF1 33 Power VDD_DIFF2 39 Power Pin Description Type ...
Page 18
... IDT82V3380A Table 1: Pin Description (Continued) Name Pin No. I/O DGND1 11 DGND2 15 DGND3 14 DGND4 49 Ground DGND5 62 DGND6 84 DGND7 87 AGND1 5 AGND2 20 Ground AGND3 92 GND_DIFF1 32 Ground GND_DIFF2 38 Ground GND_AMI 29 Ground AGND 1 Ground IC1 3 IC2 4 IC3 17 IC4 22 - IC5 96 IC6 97 IC7 Note: 1. All the unused input pins should be connected to ground; the output of all the unused output pins are don’t-care. ...
Page 19
... IDT82V3380A 3 FUNCTIONAL DESCRIPTION 3.1 RESET The reset operation resets all registers and state machines to their default value or status. After power on, the device must be reset for normal operation. For a complete reset, the RST pin must be asserted low for at least 50 µs. After the RST pin is pulled high, the device will still be in reset state for 500 ms (typical) ...
Page 20
... During reset, the default value of the IN_SONET_SDH bit is deter- mined by the SONET/SDH pin: high for SONET and low for SDH. After reset, the input signal on the SONET/SDH pin takes no effect. IDT82V3380A supports single-ended input for differential input. Refer to Chapter 9.3.3.3 Single-Ended Input for Differential 3 ...
Page 21
... IDT82V3380A 3.4 INPUT CLOCK PRE-DIVIDER Each input clock is assigned an internal Pre-Divider. The Pre-Divider is used to divide the clock frequency down to the internal DPLL’s required input frequency, which is no more than 38.88 MHz. For IN1 and IN2, the DPLL required frequency is fixed to 8 kHz (i.e., the corresponding IN_FREQ[3:0] bits are ‘ ...
Page 22
... IDT82V3380A Table 4: Pre-Divider Function Pre-Divider Input Clock INn frequency 2 >155.52 MHz HF- Divider 2KHz, 4KHz, 8KHz, 1.544 MHz, 2.048 MHz, Divider Bypassed 6.48 MHz, 19.44 MHz, 25.92 MHz or 38.88 MHz 1.544 MHz, 2.048 MHz, 6.48 MHz, 19.44 Lock 8K Divider MHz, 25.92 MHz or 38.88 MHz Nx8kHz (2 ≤ N ≤ 19440) DivN Example: 25 MHz = 3125 x 8 kHz Note 1: Please see register description for details ...
Page 23
... IDT82V3380A 3.5 INPUT CLOCK QUALITY MONITORING The qualities of all the input clocks are always monitored in the fol- lowing aspects: • LOS (loss of signal) (only for IN1 and IN2) • Activity • Frequency LOS monitoring is only conducted on IN1 and IN2. Activity and fre- quency monitoring are conducted on all the input clocks ...
Page 24
... IDT82V3380A 3.5.3 FREQUENCY MONITORING Frequency is monitored by comparing the input clock with a refer- ence clock. The reference clock can be derived from the master clock or the output of T0 DPLL, as determined by the FREQ_MON_CLK bit. A frequency hard alarm threshold is set for frequency monitoring. If the FREQ_MON_HARD_EN bit is ‘1’, a frequency hard alarm is raised when the frequency of the input clock with respect to the reference clock is above the threshold ...
Page 25
... IDT82V3380A 3 DPLL INPUT CLOCK SELECTION An input clock is selected for T0 DPLL and for T4 DPLL respectively. For T0 path, the EXT_SW bit and the T0_INPUT_SEL[3:0] bits deter- mine the input clock selection, as shown in Table 7: Input Clock Selection for T0 Path Control Bits EXT_SW T0_INPUT_SEL[3:0] 1 don’ ...
Page 26
... IDT82V3380A 3.6.2 FORCED SELECTION In Forced selection, the selected input clock is set by the T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Moni- toring) do not affect the input clock selection. 3.6.3 AUTOMATIC SELECTION In Automatic selection, the input clock selection is determined by its validity, priority and locking allowance configuration ...
Page 27
... IDT82V3380A 3.7 SELECTED INPUT CLOCK MONITORING The quality of the selected input clock is always monitored (refer to Chapter 3.5 Input Clock Quality Monitoring) and the DPLL locking status is always monitored. 3.7 DPLL LOCKING DETECTION The following events is always monitored: • Fast Loss; • Coarse Phase Loss; ...
Page 28
... IDT82V3380A 3.7.3 PHASE LOCK ALARM (T0 ONLY) A phase lock alarm will be raised when the selected input clock can not be locked in T0 DPLL within a certain period. This period can be cal- culated as follows: Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0] The phase lock alarm is indicated by the corresponding INn_PH_LOCK_ALARM bit (14 ≥ n ≥ 1). ...
Page 29
... IDT82V3380A 3.8 SELECTED INPUT CLOCK SWITCH If the input clock is selected by External Fast selection or by Forced selection, it can be switched by setting the related registers (refer to Chapter 3.6.1 External Fast Selection (T0 only) Selection) any time. In this case, whether the input clock is qualified for DPLL locking does not affect the clock switch. If the T4 selected input clock DPLL output, it can only be switched by setting the T0_FOR_T4 bit ...
Page 30
... IDT82V3380A 3.8.2.2 Non-Revertive Switch (T0 only) In Non-Revertive switch, the T0 selected input clock is not switched when another qualified input clock with a higher priority than the current selected input clock is available. In this case, the selected input clock is switched and a qualified input clock with the highest priority is selected only when the T0 selected input clock is disqualified ...
Page 31
... IDT82V3380A 3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE The operating modes supported by T0 DPLL are more complex than the ones supported by T4 DPLL for T0 path is the main one. T0 DPLL supports three primary operating modes: Free-Run, Locked and Hold- over, and three secondary, temporary operating modes: Pre-Locked, Pre-Locked2 and Lost-Phase ...
Page 32
... IDT82V3380A 15 Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode Notes to Figure 7: 1. Reset input clock is selected. 3. The T0 selected input clock is disqualified AND No qualified input clock is available. 4. The T0 selected input clock is switched to another one. 5. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’). ...
Page 33
... IDT82V3380A The causes of Item ‘the T0 selected input clock is switched to another one’ - are: (The T0 selected input clock is disquali- fied AND Another input clock is switched to) OR (In Revertive switch, a qualified input clock with a higher priority is switched to) OR (The T0 selected input clock is switched to another one by External Fast selec- tion or Forced selection) ...
Page 34
... IDT82V3380A 3. DPLL OPERATING MODE The T0/T4 DPLL gives a stable performance in different applications without being affected by operating conditions or silicon process varia- tions. It integrates a PFD (Phase & Frequency Detector), a LPF (Low Pass Filter) and a DCO (Digital Controlled Oscillator), which forms a closed loop input clock is selected, the loop is not closed, and the PFD and LPF do not function ...
Page 35
... IDT82V3380A is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the FAST_AVG bit, as shown in Table 20: Table 20: Frequency Offset Control in Holdover Mode MAN_HOLDOVER AUTO_AVG 0 1 3.10.1.5.1 Automatic Instantaneous By this method, the T0 DPLL freezes at the operating frequency when it enters Holdover mode. The accuracy is 4.4X10 3.10.1.5.2 Automatic Slow Averaged By this method, an internal IIR (Infinite Impulse Response) filter is employed to get the frequency offset ...
Page 36
... IDT82V3380A Table 22: Related Bit / Register in Chapter 3.10 Bit CURRENT_PH_DATA[15:0] CURRENT_DPLL_FREQ[23:0] T0_DPLL_START_BW[4:0] T0_DPLL_START_DAMPING[2:0] T0_DPLL_ACQ_BW[4:0] T0_DPLL_ACQ_DAMPING[2:0] T0_DPLL_LOCKED_BW[4:0] T0_DPLL_LOCKED_DAMPING[2:0] AUTO_BW_SEL FAST_LOS_SW TEMP_HOLDOVER_MODE[1:0] MAN_HOLDOVER AUTO_AVG FAST_AVG READ_AVG T0_HOLDOVER_FREQ[23:0] T4_DPLL_LOCKED_BW[1:0] T4_DPLL_LOCKED_DAMPING[2:0] T4_T0_SEL Note: * The setting in the 5B 64, 68 and 69 registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit. ...
Page 37
... IDT82V3380A 3. DPLL OUTPUT The DPLL output is locked to the selected input clock. According to the phase-compared result of the feedback and the selected input clock, and the DPLL output frequency offset, the PFD output is limited and the DPLL output is frequency offset limited. 3.11.1 PFD OUTPUT LIMIT The PFD output is limited to be within ± ...
Page 38
... IDT82V3380A 3.11.5.2 T4 Path The four paths for T4 DPLL output are as follows: • 77.76 MHz path - outputs a 77.76 MHz clock; • 16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by the IN_SONET_SDH bit; • GSM/GPS/16E1/16T1 path - outputs an GSM, GPS, 16E1 or 16T1 clock, as selected by the T4_GSM_GPS_16E1_16T1_ SEL[1:0] bits; ...
Page 39
... IDT82V3380A 3. APLL A T0 APLL and a T4 APLL are provided for a better jitter and wander performance of the device output clocks. The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0] / T4_APLL_BW[1:0] bits respectively. The lower the bandwidth is, the better the jitter and wander performance of the T0/T4 APLL output are. ...
Page 40
... IDT82V3380A Table 25: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 DPLL Outputs OUTn_DIVIDER[3:0] 1 (Output Divider) 77.76 MHz 12E1 0000 0001 0010 77.76 MHz 12E1 0011 6E1 0100 3E1 0101 2E1 0110 0111 E1 1000 1001 1010 64 kHz 1011 8 kHz 1100 2 kHz 1101 400 Hz 1110 1Hz 1111 Note ≤ ...
Page 41
... IDT82V3380A Table 26: Outputs on OUT1 ~ OUT7 if Derived from T0 APLL OUTn_DIVIDER[3:0] 1 (Output Divider) 77.76 MHz X 4 0000 3 0001 622.08 MHz 3 0010 311.04 MHz 0011 155.52 MHz 0100 77.76 MHz 0101 51.84 MHz 0110 38.88 MHz 0111 25.92 MHz 1000 19.44 MHz 1001 1010 1011 6.48 MHz 1100 1101 1110 1111 Note ≤ ...
Page 42
... IDT82V3380A Table 27: Outputs on OUT1 & 2 & 4 & 5 & Derived from T4 APLL OUTn_DIVIDER[3 (Output Divider) 77.76 MHz X 4 0000 3 0001 622.08 MHz 3 0010 311.04 MHz 0011 155.52 MHz 0100 77.76 MHz 0101 51.84 MHz 0110 38.88 MHz 0111 25.92 MHz 1000 19.44 MHz 1001 1010 1011 6.48 MHz ...
Page 43
... IDT82V3380A Table 28: Outputs on OUT3 & OUT7 if Derived from T4 APLL OUTn_DIVIDER[3 :0] (Output 1 77.76 MHz X 4 12E1 X 4 16E1 X 4 24T1 X 4 16T1 X 4 Divider) 0000 3 0001 622.08 MHz 3 0010 48E1 311.04 MHz 0011 155.52 MHz 24E1 0100 77.76 MHz 12E1 0101 51.84 MHz 8E1 0110 38 ...
Page 44
... IDT82V3380A 3.13.2 FRAME SYNC OUTPUT SIGNALS An 8 kHz and a 2 kHz frame sync signals are output on the FRSYNC_8K and MFRSYNC_2K pins if enabled by the 8K_EN and 2K_EN bits respectively. They are CMOS outputs. The two frame sync signals are derived from the T0 APLL output and are aligned with the output clock ...
Page 45
... IDT82V3380A T0 selected input clock EX_SYNC1 Frame sync output signals Output clocks Figure 11. 0.5 UI Late Frame Sync Input Signal Timing T0 selected input clock EX_SYNC1 Frame sync output signals Output clocks Figure 12 Late Frame Sync Input Signal Timing Functional Description SYNCHRONOUS ETHERNET WAN PLL™ ...
Page 46
... IDT82V3380A Table 31: Related Bit / Register in Chapter 3.13 Bit OUT6_PECL_LVDS OUT7_PECL_LVDS OUTn_PATH_SEL[3:0] (1 ≤ n ≤ 7) OUTn_DIVIDER[3:0] (1 ≤ n ≤ 7) OUT8_PATH_SEL 400HZ_SEL AMI_OUT_DUTY 1 T4_INPUT_FAIL OUT8_EN OUT9_PATH_SEL OUT9_EN 2 T4_INPUT_FAIL IN_SONET_SDH AUTO_EXT_SYNC_EN EXT_SYNC_EN OUTn_INV (1 ≤ n ≤ 8K_EN 2K_EN 8K_INV 2K_INV 8K_PUL 2K_PUL 2K_8K_PUL_POSITION SYNC_MON_LIMT[2:0] SYNC_PH1[1:0] EX_SYNC_ALARM_MON ...
Page 47
... IDT82V3380A 3.14 MASTER / SLAVE CONFIGURATION Master / Slave configuration is only supported by the T0 path of the device. Two devices should be used together in order to: • Enable system protection against single chip failure; • Guarantee no service interrupt during system maintenance, such as software or hardware upgrade. Of the two devices, one is configured as the Master and the other is configured as the Slave ...
Page 48
... IDT82V3380A 3.15 INTERRUPT SUMMARY The interrupt sources of the device are as follows: • AMI violation • LOS • T4 DPLL locking status change • Input clocks for T0 path validity change • T0 selected input clock fail • Input clocks for T4 path change qualified input clock available • ...
Page 49
... PLL. The IDT82V3380A provides separate VDDA power pins for the internal ana- log PLL, VDD_DIFF for the differential output driver circuit and VDDD pins for the core logic as well as I/O driver circuits ...
Page 50
... Slave. Refer to Chapter 3.14 Master / Slave Configuration for details. 50 SYNCHRONOUS ETHERNET WAN PLL™ BITS/SSU Timing Module Stratum 2/3E IDT82V3288 Stratum 2/3E/3/SMC/SEC Line Timing Module Eth/E1/T1/ IDT82V3380A OC-N Clock Eth/E1/T1/OC-N Clock Eth/E1/T1/OC-N Eth/E1/T1/OC-N Clock Clock . . . Line Card Line Card IDT82V3355 IDT82V3355 In Master / Slave application, two devices should be used together. ...
Page 51
... IDT82V3380A 5 MICROPROCESSOR INTERFACE The microprocessor interface provides access to read and write the registers in the device. The microprocessor interface supports the fol- lowing five modes: • EPROM mode; • Multiplexed mode; • Intel mode; • Motorola mode; • Serial mode. The microprocessor interface mode is selected by the MPU_SEL_CNFG[2:0] bits (b2~0, 7FH) ...
Page 52
... IDT82V3380A 5.1 EPROM MODE In this mode, the device is used with an EPROM. The configuration data will be automatically read from the EPROM after the device is pow- ered on. CS A[6:0] AD[7:0] High-Z Table 36: Access Timing Characteristics in EPROM Mode Symbol Parameter valid data delay time acc Microprocessor Interface ...
Page 53
... IDT82V3380A 5.2 MULTIPLEXED MODE ALE AD[7:0] High-Z RDY Table 37: Read Timing Characteristics in Multiplexed Mode Symbol T One cycle time of the master clock out t Valid address to ALE falling edge setup time su1 t Valid CS to Valid RD setup time su2 t Valid RD to valid data delay time ...
Page 54
... IDT82V3380A ALE AD[7:0] RDY Table 38: Write Timing Characteristics in Multiplexed Mode Symbol T One cycle time of the master clock out t Valid address to ALE falling edge setup time su1 t Valid CS to valid WR setup time su2 t Valid data to WR rising edge setup time su3 ...
Page 55
... IDT82V3380A 5.3 INTEL MODE A[6:0] AD[7:0] RDY Table 39: Read Timing Characteristics in Intel Mode Symbol T One cycle time of the master clock out t Valid address to valid CS setup time su1 t Valid CS to valid RD setup time su2 t Valid RD to valid data delay time d1 t Valid CS to valid RDY delay time ...
Page 56
... IDT82V3380A A[6:0] AD[7:0] RDY Table 40: Write Timing Characteristics in Intel Mode Symbol T One cycle time of the master clock out t Valid address to valid CS setup time su1 t Valid CS to valid WR setup time su2 t Valid data before WR rising edge setup time su3 t Valid CS to valid RDY delay time ...
Page 57
... IDT82V3380A 5.4 MOTOROLA MODE CS WR A[6:0] AD[7:0] RDY Table 41: Read Timing Characteristics in Motorola Mode Symbol T One cycle time of the master clock out t Valid address to valid CS setup time su1 t Valid WR to valid CS setup time su2 t Valid CS to valid data delay time d1 t Valid CS to valid RDY delay time ...
Page 58
... IDT82V3380A CS WR A[6:0] AD[7:0] RDY Table 42: Write Timing Characteristics in Motorola Mode Symbol T One cycle time of the master clock out t Valid address to valid CS setup time su1 t Valid WR to valid CS setup time su2 t Valid data before CS rising edge setup time su3 t Valid CS to valid RDY delay time ...
Page 59
... IDT82V3380A 5.5 SERIAL MODE In a read operation, the active edge of SCLK is selected by CLKE. When CLKE is asserted low, data on SDO will be clocked out on the ris su2 SCLK su1 SDI R/W A0 SDO Figure 25. Serial Read Timing Diagram (CLKE Asserted Low) CS SCLK SDI R/W A0 SDO Figure 26 ...
Page 60
... IDT82V3380A CS t su2 SCLK su1 SDI R/W A0 SDO Table 44: Write Timing Characteristics in Serial Mode Symbol T One cycle time of the master clock out t Valid SDI to valid SCLK setup time su1 t Valid CS to valid SCLK setup time su2 t SCLK pulse width low ...
Page 61
... IDT82V3380A 6 JTAG This device is compliant with the IEEE 1149.1 Boundary Scan stan- dard except the following: • The output boundary scan cells do not capture data from the core and the device does not support EXTEST instruction; • The TRST pin is set low by default and JTAG is disabled in order to be consistent with other manufacturers ...
Page 62
... IDT82V3380A 7 PROGRAMMING INFORMATION After reset, all the registers are set to their default values. The regis- ters are read or written via the microprocessor interface. Before any write operation, PROTECTION_CNFG is recommended to be confirmed to make sure whether the write operation is enabled. The device provides 3 register protection modes: • ...
Page 63
... IDT82V3380A Table 46: Register List and Map (Continued) Address Register Name (Hex) MON_SW_PBO_CNFG - Frequency 0B Monitor, Input Clock Selection & PBO Control MS_SL_CTRL_CNFG - Master Slave 13 Control PROTECTION_CNFG - Register Pro- 7E tection Mode Configuration MPU_SEL_CNFG - Microprocessor 7F Interface Mode Configuration INTERRUPT_CNFG - Interrupt Con- 0C figuration INTERRUPTS1_STS - Interrupt Status ...
Page 64
... IDT82V3380A Table 46: Register List and Map (Continued) Address Register Name (Hex) IN11_CNFG - Input Clock 11 Configu- 1F ration IN12_CNFG - Input Clock 12 Configu- 20 ration IN13_CNFG - Input Clock 13 Configu- 21 ration IN14_CNFG - Input Clock 14 Configu- 22 ration PRE_DIV_CH_CNFG - DivN Divider 23 Channel Selection PRE_DIVN[7:0]_CNFG - DivN Divider 24 Division Factor Configuration 1 ...
Page 65
... IDT82V3380A Table 46: Register List and Map (Continued) Address Register Name (Hex) UPPER_THRESHOLD_1_CNFG 35 Upper Threshold for Leaky Bucket Configuration 1 LOWER_THRESHOLD_1_CNFG 36 Lower Threshold for Leaky Bucket Configuration 1 BUCKET_SIZE_1_CNFG - Bucket 37 Size for Leaky Bucket Configuration 1 DECAY_RATE_1_CNFG - Decay Rate 38 for Leaky Bucket Configuration 1 UPPER_THRESHOLD_2_CNFG 39 Upper Threshold for Leaky Bucket ...
Page 66
... IDT82V3380A Table 46: Register List and Map (Continued) Address Register Name (Hex) IN11_IN12_STS - Input Clock 11 & Status IN13_IN14_STS - Input Clock 13 & Status INPUT_VALID1_STS - Input Clocks 4A Validity 1 INPUT_VALID2_STS - Input Clocks 4B Validity 2 REMOTE_INPUT_VALID1_CNFG 4C Input Clocks Validity Configuration 1 REMOTE_INPUT_VALID2_CNFG 4D Input Clocks Validity Configuration 2 ...
Page 67
... IDT82V3380A Table 46: Register List and Map (Continued) Address Register Name (Hex) PHASE_LOSS_FINE_LIMIT_CNFG - 5B Phase Loss Fine Detector Limit Con- figuration * T0_HOLDOVER_MODE_CNFG - T0 5C DPLL Holdover Mode Configuration T0_HOLDOVER_FREQ[7:0]_CNFG - 5D T0 DPLL Holdover Frequency Config- uration 1 T0_HOLDOVER_FREQ[15:8]_CNFG DPLL Holdover Frequency Con- figuration 2 ...
Page 68
... IDT82V3380A Table 46: Register List and Map (Continued) Address Register Name (Hex) OUT7_FREQ_CNFG - Output Clock 7 71 Frequency Configuration OUT8_FREQ_CNFG - Output Clock 8 72 Frequency Configuration & Output Clock 6, 7 & 9 Invert Configuration OUT9_FREQ_CNFG - Output Clock 9 73 Frequency Configuration & Output Clock Invert Configuration ...
Page 69
... ID[15:8] - Device ID 2 Address: 01H Type: Read Default Value: 00010001 7 6 ID15 ID14 Bit Name ID[15:8] The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V3380A. MPU_PIN_STS - MPU_MODE[2:0] Pins Status Address: 02H Type: Read Default Value: XXXXXXXX Bit Name Reserved ...
Page 70
... IDT82V3380A NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3 Address: 06H Type: Read / Write Default Value: 00000000 7 6 NOMINAL_FRE NOMINAL_FRE Q_VALUE23 Q_VALUE22 Bit Name The NOMINAL_FREQ_VALUE[23:0] bits represent a 2’s complement signed integer. If the value is multiplied by 0.0000884, the calibration value for the master clock in ppm will be gotten. ...
Page 71
... IDT82V3380A PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration Address: 08H Type: Read / Write Default Value: 00110010 7 6 MULTI_FACTO MULTI_FACTO TIME_OUT_VA R1 R0 Bit Name MULTI_FACTOR[1: TIME_OUT_VALUE[5:0] Programming Information 5 4 TIME_OUT_VA TIME_OUT_VA LUE5 LUE4 LUE3 These bits determine a factor which has a relationship with a period in seconds. A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘ ...
Page 72
... IDT82V3380A INPUT_MODE_CNFG - Input Mode Configuration Address: 09H Type: Read / Write Default Value: 10100XX0 7 6 AUTO_EXT_SY EXT_SYNC_EN NC_EN Bit Name 7 AUTO_EXT_SYNC_EN Refer to the description of the EXT_SYNC_EN bit (b6, 09H). This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether EX_SYNC1 is enabled to synchronize the frame sync output signals. ...
Page 73
... IDT82V3380A DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration Address: 0AH Type: Read / Write Default Value: XXXXX001 Bit Name Reserved. This bit selects a better active edge of the master clock. 2 OSC_EDGE 0: The rising edge. (default) 1: The falling edge. This bit selects a port technology for OUT7. ...
Page 74
... IDT82V3380A MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control Address: 0BH Type: Read / Write Default Value: 100X01X1 7 6 FREQ_MON_C LOS_FLAG_TO ULTR_FAST_SW LK _TDO Bit Name The bit selects a reference clock for input clock frequency monitoring. 7 FREQ_MON_CLK 0: The output of T0 DPLL. 1: The master clock. (default) The bit determines whether the interrupt of T0 selected input clock fail - is reported by the TDO pin ...
Page 75
... IDT82V3380A MS_SL_CTRL_CNFG - Master Slave Control Address: 13H Type: Read / Write Default Value: XXXXXXX0 Bit Name 7-1 - Reserved. These bits, together with the MS/SL pin, control whether the device is configured as the Master or as the Slave. 0 MS_SL_CTRL The default value of this bit is ‘0’. ...
Page 76
... IDT82V3380A MPU_SEL_CNFG - Microprocessor Interface Mode Configuration Address: 7FH Type: Read / Write Default Value: XXXXXXXX Bit Name Reserved. These bits select a microprocessor interface mode: 000: Reserved. 001: EPROM mode. 010: Multiplexed mode MPU_SEL_CNFG[2:0] 011: Intel mode. 100: Motorola mode. ...
Page 77
... IDT82V3380A 7.2.2 INTERRUPT REGISTERS INTERRUPT_CNFG - Interrupt Configuration Address: 0CH Type: Read / Write Default Value: XXXXXX10 Bit Name Reserved. This bit determines the output characteristics of the INT_REQ pin. 0: The output on the INT_REQ pin is high/low when the interrupt is active; the output is the opposite when the interrupt is inactive. ...
Page 78
... IDT82V3380A INTERRUPTS2_STS - Interrupt Status 2 Address: 0EH Type: Read / Write Default Value: 00111111 7 6 T0_OPERATING T0_MAIN_REF_F _MODE AILED Bit Name 7 T0_OPERATING_MODE 6 T0_MAIN_REF_FAILED INn Programming Information 5 4 IN14 IN13 This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes ...
Page 79
... IDT82V3380A INTERRUPTS3_STS - Interrupt Status 3 Address: 0FH Type: Read / Write Default Value: 11X10000 7 6 EX_SYNC_ALARM T4_STS Bit Name This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the EX_SYNC_ALARM_MON bit (b7, 52H). 7 EX_SYNC_ALARM 0: Has not occurred. ...
Page 80
... IDT82V3380A INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1 Address: 10H Type: Read / Write Default Value: 00000000 7 6 IN8 IN7 Bit Name This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn bit (b7~0, 0DH) is ‘1’. Here n is any one ...
Page 81
... IDT82V3380A INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3 Address: 12H Type: Read / Write Default Value: 00X00000 7 6 EX_SYNC_ALARM T4_STS Bit Name This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync alarm has occurred, i.e., when the EX_SYNC_ALARM bit (b7, 0FH) is ‘1’. ...
Page 82
... IDT82V3380A 7.2.3 INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS IN1_CNFG - Input Clock 1 Configuration Address: 14H Type: Read / Write Default Value: X0000000 400HZ_SEL BUCKET_SEL1 Bit Name 7 - Reserved. This bit should be set to match the clock input on IN1: 6 400HZ_SEL 0: 64 kHz + 8 kHz. (default kHz + 8 kHz + 0.4 kHz. ...
Page 83
... IDT82V3380A IN3_CNFG - Input Clock 3 Configuration Address: 16H Type: Read / Write Default Value: 00000000 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 16H). This bit, together with the DIRECT_DIV bit (b7, 16H), determines whether the DivN Divider or the Lock 8k Divider is used for ...
Page 84
... IDT82V3380A IN4_CNFG - Input Clock 4 Configuration Address: 17H Type: Read / Write Default Value: 00000000 7 6 DIRECT_DIV LOCK_8K Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 17H). This bit, together with the DIRECT_DIV bit (b7, 17H), determines whether the DivN Divider or the Lock 8k Divider is used for ...
Page 85
... IDT82V3380A IN5_IN6_HF_DIV_CNFG - Input Clock 5 & 6 High Frequency Divider Configuration Address: 18H Type: Read / Write Default Value: 00XXXX00 7 6 IN6_DIV1 IN6_DIV0 Bit Name These bits determine whether the HF Divider is used and what the division factor is for IN6 frequency division: 00: Bypassed. (default IN6_DIV[1:0] 01: Divided by 4 ...
Page 86
... IDT82V3380A IN5_CNFG - Input Clock 5 Configuration Address: 19H Type: Read / Write Default Value: 00000011 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 19H). This bit, together with the DIRECT_DIV bit (b7, 19H), determines whether the DivN Divider or the Lock 8k Divider is used for ...
Page 87
... IDT82V3380A IN6_CNFG - Input Clock 6 Configuration Address: 1AH Type: Read / Write Default Value: 00000011 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1AH). This bit, together with the DIRECT_DIV bit (b7, 1AH), determines whether the DivN Divider or the Lock 8k Divider is used for ...
Page 88
... IDT82V3380A IN7_CNFG - Input Clock 7 Configuration Address: 1BH Type: Read / Write Default Value: 00000011 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1BH). This bit, together with the DIRECT_DIV bit (b7, 1BH), determines whether the DivN Divider or the Lock 8k Divider is used for ...
Page 89
... IDT82V3380A IN8_CNFG - Input Clock 8 Configuration Address: 1CH Type: Read / Write Default Value: 00000011 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1CH). This bit, together with the DIRECT_DIV bit (b7, 1CH), determines whether the DivN Divider or the Lock 8k Divider is used for ...
Page 90
... IDT82V3380A IN9_CNFG - Input Clock 9 Configuration Address: 1DH Type: Read / Write Default Value: 00000011 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1DH). This bit, together with the DIRECT_DIV bit (b7, 1DH), determines whether the DivN Divider or the Lock 8k Divider is used for ...
Page 91
... IDT82V3380A IN10_CNFG - Input Clock 10 Configuration Address: 1EH Type: Read / Write Default Value: 00000011 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1EH). This bit, together with the DIRECT_DIV bit (b7, 1EH), determines whether the DivN Divider or the Lock 8k Divider is used for ...
Page 92
... IDT82V3380A IN11_CNFG - Input Clock 11 Configuration Address: 1FH Type: Read / Write Default Value: 0000XXXX 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1FH). This bit, together with the DIRECT_DIV bit (b7, 1FH), determines whether the DivN Divider or the Lock 8k Divider is used for ...
Page 93
... IDT82V3380A IN12_CNFG - Input Clock 12 Configuration Address: 20H Type: Read / Write Default Value: 00000001 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 20H). This bit, together with the DIRECT_DIV bit (b7, 20H), determines whether the DivN Divider or the Lock 8k Divider is used for ...
Page 94
... IDT82V3380A IN13_CNFG - Input Clock 13 Configuration Address: 21H Type: Read / Write Default Value: 00000001 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 21H). This bit, together with the DIRECT_DIV bit (b7, 21H), determines whether the DivN Divider or the Lock 8k Divider is used for ...
Page 95
... IDT82V3380A IN14_CNFG - Input Clock 14 Configuration Address: 22H Type: Read / Write Default Value: 00000001 7 6 DIRECT_DIV LOCK_8K BUCKET_SEL1 Bit Name 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 22H). This bit, together with the DIRECT_DIV bit (b7, 22H), determines whether the DivN Divider or the Lock 8k Divider is used for ...
Page 96
... IDT82V3380A PRE_DIV_CH_CNFG - DivN Divider Channel Selection Address: 23H Type: Read / Write Default Value: XXXX0000 Bit Name PRE_DIV_CH_VALUE[3:0] PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1 Address: 24H Type: Read / Write Default Value: 00000000 7 6 PRE_DIVN_VA PRE_DIVN_VA LUE7 LUE6 Bit ...
Page 97
... IDT82V3380A PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2 Address: 25H Type: Read / Write Default Value: X0000000 7 6 PRE_DIVN_VAL PRE_DIVN_VAL - UE14 Bit Name PRE_DIVN_VALUE[14:8] Programming Information 5 4 PRE_DIVN_VAL PRE_DIVN_VAL UE13 UE12 Reserved. If the value in the PRE_DIVN_VALUE[14:0] bits is plus 1, the division factor for an input clock will be gotten. The input clock is selected by the PRE_DIV_CH_VALUE[3:0] bits (b3~0, 23H). A value from ‘ ...
Page 98
... IDT82V3380A IN1_IN2_SEL_PRIORITY_CNFG - Input Clock 1 & 2 Priority Configuration * Address: 26H Type: Read / Write Default Value 00110010 / T4 - 00000000 7 6 IN2_SEL_PRIO IN2_SEL_PRIO IN2_SEL_PRIO RITY3 RITY2 Bit Name INn_SEL_PRIORITY[3: INn_SEL_PRIORITY[3:0] Programming Information 5 4 IN2_SEL_PRIO IN1_SEL_PRIO RITY1 RITY0 RITY3 These bits set the priority of the corresponding INn. Here 0000: Disable INn for automatic selection ...
Page 99
... IDT82V3380A IN3_IN4_SEL_PRIORITY_CNFG - Input Clock 3 & 4 Priority Configuration * Address: 27H Type: Read / Write Default Value 01010100 / T4 - 00000000 7 6 IN4_SEL_PRIO IN4_SEL_PRIO IN4_SEL_PRIO RITY3 RITY2 Bit Name INn_SEL_PRIORITY[3: INn_SEL_PRIORITY[3:0] Programming Information IN4_SEL_PRIO IN3_SEL_PRIO RITY1 RITY0 RITY3 These bits set the priority of the corresponding INn. Here ...
Page 100
... IDT82V3380A IN5_IN6_SEL_PRIORITY_CNFG - Input Clock 5 & 6 Priority Configuration * Address: 28H Type: Read / Write Default Value: T0/T4 - 01110110 7 6 IN6_SEL_PRIO IN6_SEL_PRIO RITY3 RITY2 Bit Name INn_SEL_PRIORITY[3: INn_SEL_PRIORITY[3:0] Programming Information 5 4 IN6_SEL_PRIO IN6_SEL_PRIO IN5_SEL_PRIO RITY1 RITY0 These bits set the priority of the corresponding INn. Here ...
Page 101
... IDT82V3380A IN7_IN8_SEL_PRIORITY_CNFG - Input Clock 7 & 8 Priority Configuration * Address: 29H Type: Read / Write Default Value: 10011000 7 6 IN8_SEL_PRIO IN8_SEL_PRIO IN8_SEL_PRIO RITY3 RITY2 Bit Name INn_SEL_PRIORITY[3: INn_SEL_PRIORITY[3:0] Programming Information 5 4 IN8_SEL_PRIO IN7_SEL_PRIO RITY1 RITY0 RITY3 These bits set the priority of the corresponding INn. Here ...
Page 102
... IDT82V3380A IN9_IN10_SEL_PRIORITY_CNFG - Input Clock 9 & 10 Priority Configuration * Address: 2AH Type: Read / Write Default Value: 10111010 7 6 IN10_SEL_PRI IN10_SEL_PRI IN10_SEL_PRI ORITY3 ORITY2 Bit Name INn_SEL_PRIORITY[3: INn_SEL_PRIORITY[3:0] Programming Information IN10_SEL_PRI IN9_SEL_PRIO ORITY1 ORITY0 RITY3 These bits set the priority of the corresponding INn. Here n is 10. ...
Page 103
... IDT82V3380A IN11_IN12_SEL_PRIORITY_CNFG - Input Clock 11 & 12 Priority Configuration * Address: 2BH Type: Read / Write Default Value: 11011100 (T0 Master)/11010001 (T0 Slave) 00000000 (T4 IN12_SEL_PRI IN12_SEL_PRI IN12_SEL_PRI ORITY3 ORITY2 Bit Name INn_SEL_PRIORITY[3: INn_SEL_PRIORITY[3:0] Programming Information 5 4 IN12_SEL_PRI IN11_SEL_PRI ORITY1 ORITY0 ORITY3 These bits set the priority of the corresponding INn. Here n is 12: 0000: Disable INn for automatic selection ...
Page 104
... IDT82V3380A IN13_IN14_SEL_PRIORITY_CNFG - Input Clock 13 & 14 Priority Configuration * Address: 2CH Type: Read / Write Default Value: 11111110 (T0) 00000000 (T4 IN14_SEL_PRI IN14_SEL_PRI IN14_SEL_PRI ORITY3 ORITY2 Bit Name INn_SEL_PRIORITY[3: INn_SEL_PRIORITY[3:0] Programming Information IN14_SEL_PRI IN13_SEL_PRI ORITY1 ORITY0 ORITY3 These bits set the priority of the corresponding INn. Here n is 14: 0000: Disable INn for automatic selection ...
Page 105
... IDT82V3380A 7.2.4 INPUT CLOCK QUALITY MONITORING CONFIGURATION & STATUS REGISTERS FREQ_MON_FACTOR_CNFG - Factor of Frequency Monitor Configuration Address: 2EH Type: Read / Write Default Value: XXXX1011 Bit Name FREQ_MON_FACTOR[3:0] ALL_FREQ_MON_THRESHOLD_CNFG - Frequency Monitor Threshold for All Input Clocks Configuration Address: 2FH Type: Read / Write ...
Page 106
... IDT82V3380A UPPER_THRESHOLD_0_CNFG - Upper Threshold for Leaky Bucket Configuration 0 Address: 31H Type: Read / Write Default Value: 00000110 7 6 UPPER_THRE UPPER_THRE SHOLD_0_DAT SHOLD_0_DAT A7 A6 Bit Name UPPER_THRESHOLD_0_DATA[7:0] LOWER_THRESHOLD_0_CNFG - Lower Threshold for Leaky Bucket Configuration 0 Address: 32H Type: Read / Write Default Value: 00000100 ...
Page 107
... IDT82V3380A DECAY_RATE_0_CNFG - Decay Rate for Leaky Bucket Configuration 0 Address: 34H Type: Read / Write Default Value: XXXXXX01 Bit Name DECAY_RATE_0_DATA[1:0] UPPER_THRESHOLD_1_CNFG - Upper Threshold for Leaky Bucket Configuration 1 Address: 35H Type: Read / Write Default Value: 00000110 7 6 UPPER_THRE UPPER_THRE SHOLD_1_DAT ...
Page 108
... IDT82V3380A BUCKET_SIZE_1_CNFG - Bucket Size for Leaky Bucket Configuration 1 Address: 37H Type: Read / Write Default Value: 00001000 7 6 BUCKET_SIZE BUCKET_SIZE BUCKET_SIZE _1_DATA7 _1_DATA6 Bit Name BUCKET_SIZE_1_DATA[7:0] DECAY_RATE_1_CNFG - Decay Rate for Leaky Bucket Configuration 1 Address: 38H Type: Read / Write Default Value: XXXXXX01 ...
Page 109
... IDT82V3380A LOWER_THRESHOLD_2_CNFG - Lower Threshold for Leaky Bucket Configuration 2 Address: 3AH Type: Read / Write Default Value: 00000100 7 6 LOWER_THRE LOWER_THRE LOWER_THRE SHOLD_2_DAT SHOLD_2_DAT SHOLD_2_DAT A7 A6 Bit Name LOWER_THRESHOLD_2_DATA[7:0] BUCKET_SIZE_2_CNFG - Bucket Size for Leaky Bucket Configuration 2 Address: 3BH Type: Read / Write Default Value: 00001000 ...
Page 110
... IDT82V3380A UPPER_THRESHOLD_3_CNFG - Upper Threshold for Leaky Bucket Configuration 3 Address: 3DH Type: Read / Write Default Value: 00000110 7 6 UPPER_THRE UPPER_THRE UPPER_THRE SHOLD_3_DAT SHOLD_3_DAT SHOLD_3_DAT A7 A6 Bit Name UPPER_THRESHOLD_3_DATA[7:0] LOWER_THRESHOLD_3_CNFG - Lower Threshold for Leaky Bucket Configuration 3 Address: 3EH Type: Read / Write Default Value: 00000100 ...
Page 111
... IDT82V3380A DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3 Address: 40H Type: Read / Write Default Value: XXXXXX01 Bit Name DECAY_RATE_3_DATA[1:0] IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel Selection Address: 41H Type: Read / Write Default Value: XXXX0000 Bit Name ...
Page 112
... IDT82V3380A IN_FREQ_READ_STS - Input Clock Frequency Read Value Address: 42H Type: Read Default Value: 00000000 7 6 IN_FREQ_VAL IN_FREQ_VAL UE7 UE6 Bit Name These bits represent a 2’s complement signed integer. If the value is multiplied by the value in the FREQ_MON_FACTOR[3:0] bits (b3~0, 2EH), the frequency of an input clock with respect to the reference clock in ppm will ...
Page 113
... IDT82V3380A IN3_IN4_STS - Input Clock 3 & 4 Status Address: 44H Type: Read Default Value: X110X110 7 6 IN4_FREQ_HAR IN4_NO_ACTIVI - D_ALARM TY_ALARM Bit Name IN4_FREQ_HARD_ALARM 5 IN4_NO_ACTIVITY_ALARM 4 IN4_PH_LOCK_ALARM IN3_FREQ_HARD_ALARM 1 IN3_NO_ACTIVITY_ALARM 0 IN3_PH_LOCK_ALARM Programming Information IN4_PH_LOCK_ - ALARM Reserved. This bit indicates whether IN4 is in frequency hard alarm status. ...
Page 114
... IDT82V3380A IN5_IN6_STS - Input Clock 5 & 6 Status Address: 45H Type: Read Default Value: X110X110 7 6 IN6_FREQ_HAR IN6_NO_ACTIVI - D_ALARM TY_ALARM Bit Name IN6_FREQ_HARD_ALARM 5 IN6_NO_ACTIVITY_ALARM 4 IN6_PH_LOCK_ALARM IN5_FREQ_HARD_ALARM 1 IN5_NO_ACTIVITY_ALARM 0 IN5_PH_LOCK_ALARM Programming Information IN6_PH_LOCK_ - ALARM Reserved. This bit indicates whether IN6 is in frequency hard alarm status. ...
Page 115
... IDT82V3380A IN7_IN8_STS - Input Clock 7 & 8 Status Address: 46H Type: Read Default Value: X110X110 7 6 IN8_FREQ_HA IN8_NO_ACTIV - RD_ALARM Bit Name IN8_FREQ_HARD_ALARM 5 IN8_NO_ACTIVITY_ALARM 4 IN8_PH_LOCK_ALARM IN7_FREQ_HARD_ALARM 1 IN7_NO_ACTIVITY_ALARM 0 IN7_PH_LOCK_ALARM Programming Information 5 4 IN8_PH_LOCK ITY_ALARM _ALARM Reserved. This bit indicates whether IN8 is in frequency hard alarm status. ...
Page 116
... IDT82V3380A IN9_IN10_STS - Input Clock 9 & 10 Status Address: 47H Type: Read Default Value: X110X110 7 6 IN10_FREQ_HA IN10_NO_ACTI - RD_ALARM VITY_ALARM Bit Name IN10_FREQ_HARD_ALARM 5 IN10_NO_ACTIVITY_ALARM 4 IN10_PH_LOCK_ALARM IN9_FREQ_HARD_ALARM 1 IN9_NO_ACTIVITY_ALARM 0 IN9_PH_LOCK_ALARM Programming Information IN10_PH_LOCK - _ALARM Reserved. This bit indicates whether IN10 is in frequency hard alarm status. ...
Page 117
... IDT82V3380A IN11_IN12_STS - Input Clock 11 & 12 Status Address: 48H Type: Read Default Value: X110X110 7 6 IN12_FREQ_H IN12_NO_ACTI - ARD_ALARM Bit Name IN12_FREQ_HARD_ALARM 5 IN12_NO_ACTIVITY_ALARM 4 IN12_PH_LOCK_ALARM IN11_FREQ_HARD_ALARM 1 IN11_NO_ACTIVITY_ALARM 0 IN11_PH_LOCK_ALARM Programming Information 5 4 IN12_PH_LOC VITY_ALARM K_ALARM Reserved. This bit indicates whether IN12 is in frequency hard alarm status. ...
Page 118
... IDT82V3380A IN13_IN14_STS - Input Clock 13 & 14 Status Address: 49H Type: Read Default Value: X110X110 7 6 IN14_FREQ_H IN14_NO_ACTI - ARD_ALARM Bit Name IN14_FREQ_HARD_ALARM 5 IN14_NO_ACTIVITY_ALARM 4 IN14_PH_LOCK_ALARM IN13_FREQ_HARD_ALARM 1 IN13_NO_ACTIVITY_ALARM 0 IN13_PH_LOCK_ALARM Programming Information 5 4 IN14_PH_LOC VITY_ALARM K_ALARM Reserved. This bit indicates whether IN14 is in frequency hard alarm status. ...
Page 119
... IDT82V3380A 7.2 DPLL INPUT CLOCK SELECTION REGISTERS INPUT_VALID1_STS - Input Clocks Validity 1 Address: 4AH Type: Read Default Value: 00000000 7 6 IN8 IN7 Bit Name This bit indicates the validity of the corresponding INn. Here n is any one INn 0: Invalid. (default) 1: Valid ...
Page 120
... IDT82V3380A REMOTE_INPUT_VALID2_CNFG - Input Clocks Validity Configuration 2 Address: 4DH Type: Read / Write Default Value: XX111111 Bit Name Reserved. This bit controls whether the corresponding INn is allowed to be locked for automatic selection. Here n is any one INn_VALID 0: Enabled. ...
Page 121
... IDT82V3380A PRIORITY_TABLE2_STS - Priority Status 2 * Address: 4FH Type: Read Default Value: 00000000 7 6 THIRD_HIGHE THIRD_HIGHE THIRD_HIGHE ST_PRIORITY_ ST_PRIORITY_ ST_PRIORITY_ VALIDATED3 VALIDATED2 Bit Name THIRD_HIGHEST_PRIORITY_VALIDATED[3: SECOND_HIGHEST_PRIORITY_VALIDATED[3:0] T0_INPUT_SEL_CNFG - T0 Selected Input Clock Configuration Address: 50H Type: Read / Write Default Value: XXXX0000 Bit ...
Page 122
... IDT82V3380A T4_INPUT_SEL_CNFG - T4 Selected Input Clock Configuration Address: 51H Type: Read / Write Default Value: X0000000 T4_LOCK_T0 T0_FOR_T4 Bit Name 7 - Reserved. This bit determines whether the T4 DPLL locks DPLL output or locks independently from the T0 DPLL. 6 T4_LOCK_T0 0: Independently from the T0 path. (default) 1: Locks to a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path. This bit is valid only when the T4_LOCK_T0 bit (b6, 51H) is ‘ ...
Page 123
... IDT82V3380A 7.2 DPLL STATE MACHINE CONTROL REGISTERS OPERATING_STS - DPLL Operating Status Address: 52H Type: Read Default Value: 10000001 7 6 EX_SYNC_ALA T4_DPLL_LO T0_DPLL_SOFT RM_MON CK _FREQ_ALARM Bit Name 7 EX_SYNC_ALARM_MON 6 T4_DPLL_LOCK 5 T0_DPLL_SOFT_FREQ_ALARM 4 T4_DPLL_SOFT_FREQ_ALARM 3 T0_DPLL_LOCK T0_DPLL_OPERATING_MODE[2:0] Programming Information T4_DPLL_SOFT T0_DPLL_LO _FREQ_ALARM CK This bit indicates whether the frame sync input signal is in external sync alarm status. ...
Page 124
... IDT82V3380A T0_OPERATING_MODE_CNFG - T0 DPLL Operating Mode Configuration Address: 53H Type: Read / Write Default Value: XXXXX000 Bit Name T0_OPERATING_MODE[2:0] T4_OPERATING_MODE_CNFG - T4 DPLL Operating Mode Configuration Address: 54H Type: Read / Write Default Value: XXXXX000 Bit Name T4_OPERATING_MODE[2:0] Programming Information ...
Page 125
... IDT82V3380A 7.2 DPLL & APLL CONFIGURATION REGISTERS T0_DPLL_APLL_PATH_CNFG - T0 DPLL & APLL Path Configuration Address: 55H Type: Read / Write Default Value: 00000X0X 7 6 T0_APLL_PATH T0_APLL_PA T0_APLL_PA 3 TH2 Bit Name T0_APLL_PATH[3: T0_ETH_OBSAI_16E1_16T1_SEL[1: T0_12E1_24T1_E3_T3_SEL[1:0] Programming Information T0_APLL_PA T0_ETH_OBSAI_ TH1 TH0 16E1_16T1_SEL1 These bits select an input to the T0 APLL ...
Page 126
... IDT82V3380A T0_DPLL_START_BW_DAMPING_CNFG - T0 DPLL Start Bandwidth & Damping Factor Configuration Address: 56H Type: Read / Write Default Value: 01101111 7 6 T0_DPLL_STA T0_DPLL_STA T0_DPLL_STA RT_DAMPING2 RT_DAMPING1 RT_DAMPING0 Bit Name T0_DPLL_START_DAMPING[2: T0_DPLL_START_BW[4:0] Programming Information T0_DPLL_STA T0_DPLL_STA RT_BW4 RT_BW3 These bits set the starting damping factor for T0 DPLL. ...
Page 127
... IDT82V3380A T0_DPLL_ACQ_BW_DAMPING_CNFG - T0 DPLL Acquisition Bandwidth & Damping Factor Configuration Address: 57H Type: Read / Write Default Value: 01101111 7 6 T0_DPLL_ACQ T0_DPLL_ACQ T0_DPLL_ACQ _DAMPING2 _DAMPING1 Bit Name T0_DPLL_ACQ_DAMPING[2: T0_DPLL_ACQ_BW[4:0] Programming Information 5 4 T0_DPLL_ACQ T0_DPLL_ACQ _DAMPING0 _BW4 _BW3 These bits set the acquisition damping factor for T0 DPLL. ...
Page 128
... IDT82V3380A T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration Address: 58H Type: Read / Write Default Value: 01101011 7 6 T0_DPLL_LOCK T0_DPLL_LOCK T0_DPLL_LOCK ED_DAMPING2 ED_DAMPING1 Bit Name T0_DPLL_LOCKED_DAMPING[2: T0_DPLL_LOCKED_BW[4:0] Programming Information 5 4 T0_DPLL_LOC T0_DPLL_LOC ED_DAMPING0 KED_BW4 KED_BW3 These bits set the locked damping factor for T0 DPLL. ...
Page 129
... IDT82V3380A T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configuration Address: 59H Type: Read / Write Default Value: 1XXX1XXX 7 6 AUTO_BW_SEL - Bit Name This bit determines whether starting or acquisition bandwidth / damping factor is used for T0 DPLL. 0: The starting and acquisition bandwidths / damping factors are not used. Only the locked bandwidth / damping factor is used ...
Page 130
... IDT82V3380A PHASE_LOSS_COARSE_LIMIT_CNFG - Phase Loss Coarse Detector Limit Configuration * Address: 5AH Type: Read / Write Default Value: 10000101 7 6 COARSE_PH_L WIDE_EN MULTI_PH_APP OS_LIMT_EN Bit Name This bit controls whether the occurrence of the coarse phase loss will result in the T0/T4 DPLL unlocked. 7 COARSE_PH_LOS_LIMT_EN 0: Disabled. 1: Enabled. (default) ...
Page 131
... IDT82V3380A PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Configuration * Address: 5BH Type: Read / Write Default Value: 10XXX010 7 6 FINE_PH_LOS_ FAST_LOS_SW LIMT_EN Bit Name 7 FINE_PH_LOS_LIMT_EN 6 FAST_LOS_SW PH_LOS_FINE_LIMT[2:0] Programming Information This bit controls whether the occurrence of the fine phase loss will result in the T0/T4 DPLL unlocked. ...
Page 132
... IDT82V3380A T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration Address: 5CH Type: Read / Write Default Value: 010001XX 7 6 MAN_HOLDOV AUTO_AVG ER Bit Name 7 MAN_HOLDOVER 6 AUTO_AVG 5 FAST_AVG 4 READ_AVG TEMP_HOLDOVER_MODE[1: T0_HOLDOVER_FREQ[7:0]_CNFG - T0 DPLL Holdover Frequency Configuration 1 Address: 5DH Type: Read / Write Default Value: 00000000 7 6 T0_HOLDOVER ...
Page 133
... IDT82V3380A T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2 Address: 5EH Type: Read / Write Default Value: 00000000 7 6 T0_HOLDOVER T0_HOLDOVER T0_HOLDOVER _FREQ15 _FREQ14 Bit Name T0_HOLDOVER_FREQ[15:8] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH). T0_HOLDOVER_FREQ[23:16]_CNFG - T0 DPLL Holdover Frequency Configuration 3 Address: 5FH Type: Read / Write ...
Page 134
... IDT82V3380A T4_DPLL_APLL_PATH_CNFG - T4 DPLL & APLL Path Configuration Address: 60H Type: Read / Write Default Value: 01000X0X 7 6 T4_APLL_PATH T4_APLL_PA T4_APLL_PA 3 TH2 Bit Name T4_APLL_PATH[3: T4_GSM_GPS_16E1_16T1_SEL[1: T4_12E1_24T1_E3_T3_SEL[1:0] Programming Information T4_APLL_PA T4_GSM_GPS_16 TH1 TH0 E1_16T1_SEL1 These bits select an input to the T4 APLL. ...
Page 135
... IDT82V3380A T4_DPLL_LOCKED_BW_DAMPING_CNFG - T4 DPLL Locked Bandwidth & Damping Factor Configuration Address: 61H Type: Read / Write Default Value: 011XXX00 7 6 T4_DPLL_LOCK T4_DPLL_LOCK T4_DPLL_LOCK ED_DAMPING2 ED_DAMPING1 ED_DAMPING0 Bit Name T4_DPLL_LOCKED_DAMPING[2: T4_DPLL_LOCKED_BW[1:0] CURRENT_DPLL_FREQ[7:0]_STS - DPLL Current Frequency Status 1 * Address: 62H Type: Read ...
Page 136
... IDT82V3380A CURRENT_DPLL_FREQ[23:16]_STS - DPLL Current Frequency Status 3 * Address: 64H Type: Read Default Value: 00000000 7 6 CURRENT_DP CURRENT_DP CURRENT_DP LL_FREQ23 LL_FREQ22 Bit Name CURRENT_DPLL_FREQ[23:16] DPLL_FREQ_SOFT_LIMIT_CNFG - DPLL Soft Limit Configuration Address: 65H Type: Read / Write Default Value: 10001100 7 6 FREQ_LIMT_P DPLL_FREQ_S H_LOS ...
Page 137
... IDT82V3380A DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2 Address: 67H Type: Read / Write Default Value: 00011001 7 6 DPLL_FREQ_H DPLL_FREQ_H ARD_LIMT15 ARD_LIMT14 Bit Name DPLL_FREQ_HARD_LIMT[15:8] CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1 * Address: 68H Type: Read Default Value: 00000000 7 6 CURRENT_PH CURRENT_PH CURRENT_PH ...
Page 138
... IDT82V3380A T0_T4_APLL_BW_CNFG - APLL Bandwidth Configuration Address: 6AH Type: Read / Write Default Value: XX01XX01 T0_APLL_BW1 Bit Name Reserved. These bits set the bandwidth for T0 APLL. 00: 100 kHz T0_APLL_BW[1:0] 01: 500 kHz. (default) 10: 1 MHz. 11: 2 MHz Reserved. These bits set the bandwidth for T4 APLL. ...
Page 139
... IDT82V3380A 7.2.8 OUTPUT CONFIGURATION REGISTERS OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration Address: 6BH Type: Read / Write Default Value: 00001011 7 6 OUT1_PATH_S OUT1_PATH_S OUT1_PATH_S EL3 EL2 Bit Name These bits select an input to OUT1. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. ...
Page 140
... IDT82V3380A OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration Address: 6CH Type: Read / Write Default Value: 00000110 7 6 OUT2_PATH_S OUT2_PATH_S OUT2_PATH_S EL3 EL2 Bit Name OUT2_PATH_SEL[3: OUT2_DIVIDER[3:0] Programming Information 5 4 OUT2_PATH_S OUT2_DIVIDER EL1 EL0 These bits select an input to OUT2. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77 ...
Page 141
... IDT82V3380A OUT3_FREQ_CNFG - Output Clock 3 Frequency Configuration Address: 6DH Type: Read / Write Default Value: 00001000 7 6 OUT3_PATH_S OUT3_PATH_S OUT3_PATH_S EL3 EL2 Bit Name These bits select an input to OUT3. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. ...
Page 142
... IDT82V3380A OUT4_FREQ_CNFG - Output Clock 4 Frequency Configuration Address: 6EH Type: Read / Write Default Value: 00000110 7 6 OUT4_PATH_S OUT4_PATH_S OUT4_PATH_S EL3 EL2 Bit Name These bits select an input to OUT4. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. ...
Page 143
... IDT82V3380A OUT5_FREQ_CNFG - Output Clock 5 Frequency Configuration Address: 6FH Type: Read / Write Default Value: 00000100 7 6 OUT5_PATH_S OUT5_PATH_S OUT5_PATH_S EL3 EL2 Bit Name These bits select an input to OUT5. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. ...
Page 144
... IDT82V3380A OUT6_FREQ_CNFG - Output Clock 6 Frequency Configuration Address:70H Type: Read / Write Default Value: 00000110 7 6 OUT6_PATH_S OUT6_PATH_S OUT6_PATH_S EL3 EL2 Bit Name These bits select an input to OUT6. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. ...
Page 145
... IDT82V3380A OUT7_FREQ_CNFG - Output Clock 7 Frequency Configuration Address:71H Type: Read / Write Default Value: 00001000 7 6 OUT7_PATH_S OUT7_PATH_S OUT7_PATH_S EL3 EL2 Bit Name These bits select an input to OUT7. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. ...
Page 146
... IDT82V3380A OUT8_FREQ_CNFG - Output Clock 8 Frequency Configuration & Output Clock 6, 7 & 9 Invert Configuration Address:72H Type: Read / Write Default Value: 01000000 7 6 OUT8_PATH_S OUT8_EN EL Bit Name These bits select an input to OUT8. 7 OUT8_PATH_SEL 0: The output of T4 DPLL 77.76 MHz path. (default) 1: The output of T0 DPLL 77.76 MHz path. ...
Page 147
... IDT82V3380A OUT9_FREQ_CNFG - Output Clock 9 Frequency Configuration & Output Clock Invert Configuration Address:73H Type: Read / Write Default Value: 01000000 7 6 OUT9_PATH_S OUT9_EN EL Bit Name These bits select an input to OUT9. 7 OUT9_PATH_SEL 0: The output of T4 DPLL 16E1/16T1 path. (default) 1: The output of T0 DPLL 16E1/16T1 path. ...
Page 148
... IDT82V3380A FR_MFR_SYNC_CNFG - Frame Sync & Multiframe Sync Output Configuration Address:74H Type: Read / Write Default Value: 01100000 7 6 IN_2K_4K_8K_I 8K_EN NV Bit Name 7 IN_2K_4K_8K_INV 6 8K_EN 5 2K_EN 4 2K_8K_PUL_POSITION 3 8K_INV 2 8K_PUL 1 2K_INV 0 2K_PUL Programming Information 5 4 2K_8K_PUL_P 2K_EN 8K_INV OSITION This bit determines whether the input clock is inverted before locked by the T0/T4 DPLL when the input clock is 2 kHz, 4 kHz or 8 kHz ...
Page 149
... IDT82V3380A 7.2.9 PBO & PHASE OFFSET CONTROL REGISTERS PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration Address:78H Type: Read / Write Default Value: 0X000110 7 6 IN_NOISE_WIN - DOW Bit Name 7 IN_NOISE_WINDOW PH_MON_EN 4 PH_MON_PBO_EN PH_TR_MON_LIMT[3:0] PHASE_OFFSET[7:0]_CNFG - Phase Offset Configuration 1 Address:7AH Type: Read / Write ...
Page 150
... IDT82V3380A PHASE_OFFSET[9:8]_CNFG - Phase Offset Configuration 2 Address:7BH Type: Read / Write Default Value: 0XXXXX00 7 6 PH_OFFSET_E - N Bit Name This bit determines whether the input-to-output phase offset is enabled. If the device is configured as the Master, the input-to-output phase offset: 7 PH_OFFSET_EN 0: Disabled. (default) 1: Enabled. ...
Page 151
... IDT82V3380A 7.2.10 SYNCHRONIZATION CONFIGURATION REGISTERS SYNC_MONITOR_CNFG - Sync Monitor Configuration Address:7CH Type: Read / Write Default Value: X0101011 SYNC_MON_LIMT2 Bit Name 7 - Reserved. These bits set the limit for the external sync alarm. 000: ±1 UI. 001: ±2 UI. 010: ±3 UI. (default SYNC_MON_LIMT[2:0] 011: ±4 UI. ...
Page 152
... IDT82V3380A 8 THERMAL MANAGEMENT The device operates over the industry temperature range -40°C ~ +85°C. To ensure the functionality and reliability of the device, the maxi- mum junction temperature T should not exceed 125°C. In some jmax applications, the device will consume more power and a thermal solution ...
Page 153
... IDT82V3380A 8.4 TQFP EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corre- sponding to the exposed metal pad or exposed heat slug on the pack- ...
Page 154
... IDT82V3380A 9 ELECTRICAL SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATING Table 49: Absolute Maximum Rating Symbol OUT T Ambient Operating Temperature Range A T STOR 9.2 RECOMMENDED OPERATION CONDITIONS Table 50: Recommended Operation Conditions Symbol Parameter V Power Supply (DC voltage) VDD DD T Ambient Temperature Range A I Supply Current DD P Total Power Dissipation ...
Page 155
... IDT82V3380A 9.3 I/O SPECIFICATIONS 9.3.1 AMI INPUT / OUTPUT PORT 9.3.1.1 Structure Violation Violation 8 kHz (125 µs) 9.3.1.2 I/O Level 15.6 µs 7.8 µ Signal structure of 64 kHz / 8 kHz central clock interface after suitable transformer Figure 32. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Sig- nal Input Level ...
Page 156
... IDT82V3380A AMI input AMI input For a transformer with a turns ratio of 1:1, a 3:1 ratio potential divider R to achieve the required 1 V pk-pk voltage level for the positive and negative pulses. Figure 34. AMI Input / Output Port Line Termination (Recommended) Table 51: AMI Input / Output Port Electrical Characteristics ...
Page 157
... IDT82V3380A 9.3.1.3 Over-Voltage Protection The device may require over-voltage protection on AMI input ports according to ITU Recommendation K.41. 9.3.2 CMOS INPUT / OUTPUT PORT From Table 52 to Table 55 3 Table 52: CMOS Input Port Electrical Characteristics Parameter Description V Input Voltage High IH V Input Voltage Low IL I Input Current ...
Page 158
... IDT82V3380A 9.3.3 PECL / LVDS INPUT / OUTPUT PORT 9.3.3.1 PECL Input / Output Port 130 Ω 50 Ω (transmission line) 82 Ω 2 kHz to 667 MHz 130 Ω 50 Ω (transmission line) 82 Ω 3 130 Ω 50 Ω (transmission line) 82 Ω 2 kHz to 667 MHz 130 Ω 50 Ω (transmission line) 82 Ω ...
Page 159
... IDT82V3380A Table 56: PECL Input / Output Port Electrical Characteristics Parameter Description V Input Low Voltage, Differential Inputs IL V Input High Voltage, Differential Inputs IH V Input Differential Voltage ID V Input Low Voltage, Single-ended Input IL_S V Input High Voltage, Single-ended Input IH_S I Input High Current, Input Differential Voltage V ...
Page 160
... IDT82V3380A 9.3.3.2 LVDS Input / Output Port 50 Ω (transmission line) 2 kHz 100 Ω to 667 MHz 50 Ω (transmission line) 50 Ω (transmission line) 2 kHz to 100 Ω 667 MHz 50 Ω (transmission line) Figure 37. Recommended LVDS Input Port Line Termi- nation Table 57: LVDS Input / Output Port Electrical Characteristics ...
Page 161
... IDT82V3380A 9.3.3.3 Single-Ended Input for Differential Input This is a recommended and tested interface circuit to drive differen- tial input with a single-ended signal. VCC = 3 Ω Driver_LVCMOS Figure 39. Example of Single-Ended Signal to Drive Differential Input Vth = VCC*[R2/(R1+R2)] For the example in Figure 39 R2, so Vth = VCC/2 =1.65 V ...
Page 162
... IDT82V3380A 9.4 JITTER & WANDER PERFORMANCE Table 58: Output Clock Jitter Generation 1 Test Definition 25 MHz with T4 APLL 125 MHz with T4 APLL 156.25 MHz with T4 APLL N x 2.048 MHz without APLL N x 2.048 MHz with T0/T4 APLL N x 1.544 MHz without APLL N x 1.544 MHz with T0/T4 APLL 44 ...
Page 163
... IDT82V3380A Table 59: Output Clock Phase Noise 1 Output Clock 622.08 MHz (T0 DPLL + T0/T4 APLL) 155.52 MHz (T0 DPLL + T0/T4 APLL) 25 MHz (T0 DPLL + T4 APLL) 125 MHz (T0 DPLL + T4 APLL) 156.25 MHz (T0 DPLL + T4 APLL) 38.88 MHz (T0 DPLL + T0/T4 APLL) 62.5 MHz (T0 DPLL + T4 APLL) 16E1 (T0/T4 APLL) 16T1 (T0/T4 APLL) E3 (T0/T4 APLL) T3 (T0/T4 APLL) 77.76 MHz (T4 DPLL) Note: 1 ...
Page 164
... IDT82V3380A Table 64: T0 DPLL Jitter Transfer & Damping Factor 3 dB Bandwidth Programmable Damping Factor 0.5 mHz 1 mHz 2 mHz 4 mHz 8 mHz 15 mHz 30 mHz 60 mHz 0.1 Hz 0.3 Hz 0.6 Hz 1 560 Hz Electrical Specifications Table 65: T4 DPLL Jitter Transfer & Damping Factor 1.2, 2. ...
Page 165
... IDT82V3380A 9.5 OUTPUT WANDER GENERATION template tested result Electrical Specifications Figure 40. Output Wander Generation 165 SYNCHRONOUS ETHERNET WAN PLL™ template tested result September 30, 2010 ...
Page 166
... IDT82V3380A 9.6 INPUT / OUTPUT CLOCK TIMING The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs. 8 kHz Input Clock 8 kHz Output Clock 6.48 MHz Input Clock 6.48 MHz Output Clock 19.44 MHz Input Clock 19.44 MHz Output Clock 25 ...
Page 167
... IDT82V3380A 9.7 OUTPUT CLOCK TIMING Electrical Specifications _2K _8K 156.25 (156. (1.544 (2.048 (34.368 (44.736 ...
Page 168
... IDT82V3380A Table 67: Output Clock Timing Symbol Electrical Specifications Typical Delay (ns 168 SYNCHRONOUS ETHERNET WAN PLL™ Peak to Peak Delay Variation (ns) ...
Page 169
ADSL --- APLL --- ATM --- BITS --- CMOS --- DCO --- DPLL --- DSL --- DSLAM --- DWDM --- EPROM --- ETH --- GPS --- GSM --- IIR --- IP --- ISDN --- JTAG --- LPF --- ...
Page 170
... IDT82V3380A PDH --- PECL --- PFD --- PLL --- RMS --- PRS --- SDH --- SEC --- SMC --- SONET --- SSU --- STM --- TCM-ISDN --- TDEV --- UI --- --- WLL Glossary Plesiochronous Digital Hierarchy Positive Emitter Coupled Logic Phase & Frequency Detector Phase Locked Loop Root Mean Square Primary Reference Source Synchronous Digital Hierarchy SDH / SONET Equipment Clock ...
Page 171
A AMI Violation ...................................................................................... 20 Averaged Phase Error ........................................................................ 34 B Bandwidths and Damping Factors ..................................................... 34 Acquisition Bandwidth and Damping Factor ............................... 34 Locked Bandwidth and Damping Factor ..................................... 34 Starting Bandwidth and Damping Factor .................................... 34 C Calibration ...
Page 172
... IDT82V3380A P PBO .................................................................................................... 37 PFD .................................................................................................... 34 Phase Lock Alarm ....................................................................... 28 Phase Offset ....................................................................................... 37 Phase-compared ......................................................................... 27 Phase-time ......................................................................................... 37 Pre-Divider ......................................................................................... 21 DivN Divider ................................................................................ 21 HF Divider ................................................................................... 21 Lock 8k Divider ........................................................................... 21 Index SYNCHRONOUS ETHERNET WAN PLL™ R Reference Clock ................................................................................ Selected Input Clock Switch .............................................................. 29 Non-Revertive switch ................................................................. 30 Revertive switch ......................................................................... State Machine ..............................................................................31 V Validity ............................................................................................... 29 172 , 33 September 30, 2010 ...
Page 173
... IDT82V3380A PACKAGE DIMENSIONS Figure 42. 100-Pin EQG Package Dimensions (a) (in Millimeters) SYNCHRONOUS ETHERNET WAN PLL™ 173 September 30, 2010 ...
Page 174
... IDT82V3380A Figure 43. 100-Pin EQG Package Dimensions (b) (in Millimeters) SYNCHRONOUS ETHERNET WAN PLL™ 174 September 30, 2010 ...
Page 175
... IDT82V3380A Figure 44. EQG100 Recommended Land Pattern with Exposed Pad (in Millimeters) SYNCHRONOUS ETHERNET WAN PLL™ 175 September 30, 2010 ...
Page 176
... IDT82V3380A ORDERING INFORMATION XXXXXXX XX XXXXXXX XX Device Type Device Type DATASHEET DOCUMENT HISTORY 03/23/09 Pages 13,14 05/19/09 Pages 14, 20, 160 03/11/10 Page 162 07/29/10 Pages 15, 16, 21, 22, 47, 51, 97 09/30/10 Pages 53, 55, 57, 59 Process/ Process/ Temperature Temperature Range Range Blank Industrial (-40 °C to +85 °C) Blank Industrial (-40 °C to +85 °C) ...
Page 177
... IDT82V3380A We’ve Got Your Timing Solution 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this doc- ument, including descriptions of product features and performance, is subject to change without notice ...