IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 58

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IDT82V3380AEQGBLANK

Manufacturer Part Number
IDT82V3380AEQGBLANK
Description
Manufacturer
IDT [Integrated Device Technology]
Datasheet
Table 42: Write Timing Characteristics in Motorola Mode
Microprocessor Interface
IDT82V3380A
Symbol
t
t
t
t
t
t
pw1
pw2
t
t
t
t
t
t
t
su1
su2
su3
t
t
out
T
d2
d4
h1
h2
h3
h4
r1
TI
in
Time between consecutive Write-Write or Write-Read accesses
AD[7:0]
A[6:0]
WR
Valid address after valid CS rising edge hold time
RDY
CS
Valid data after valid CS rising edge hold time
Valid WR after valid CS rising edge hold time
Valid data before CS rising edge setup time
CS rising edge to RDY release delay time
Valid CS after RDY falling edge hold time
Valid address to valid CS setup time
(CS rising edge to CS falling edge)
One cycle time of the master clock
Valid CS to valid RDY delay time
Valid WR to valid CS setup time
Valid RDY pulse width high
Valid CS pulse width low
Delay of output pad
Delay of input pad
RDY release time
High-Z
Parameter
Figure 24. Motorola Write Timing Diagram
t
su1
t
su2
t
d2
address
58
t
pw2
t
pw1
1.5T + 10
1.5T + 10
t
su3
> 7T
Min
0
0
3
0
0
0
9
data
t
h3
SYNCHRONOUS ETHERNET WAN PLL™
t
h1
t
12.86
d4
Typ
13
13
t
5
5
3
h4
t
h2
t
r1
High-Z
Max
May 16, 2011
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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