IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 80

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1
INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2
Programming Information
IDT82V3380A
Address: 11H
Type: Read / Write
Default Value: 00000000
Address: 10H
Type: Read / Write
Default Value: 00000000
T0_OPERATING
5 - 0
7 - 0
Bit
Bit
7
6
_MODE
IN8
7
7
T0_OPERATING_MODE
T0_MAIN_REF_FAILED
Name
INn
T0_MAIN_REF_F
Name
INn
IN7
6
AILED
6
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from
‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn bit (b7~0, 0DH) is ‘1’. Here n is any one of 8 to 1.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 DPLL operating mode
switches, i.e., when the T0_OPERATING_MODE bit (b7, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 selected input clock
has failed; i.e., when the T0_MAIN_REF_FAILED bit (b6, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity
changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn bit (b5~0, 0EH) is ‘1’. Here n
is any one of 14 to 9.
0: Disabled. (default)
1: Enabled.
IN6
5
IN14
5
IN5
4
IN13
4
80
IN4
IN12
3
3
Description
Description
IN3
IN11
2
SYNCHRONOUS ETHERNET WAN PLL™
2
IN10
IN2
1
1
May 16, 2011
IN9
IN1
0
0