IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 37

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

3.11
the phase-compared result of the feedback and the selected input clock,
and the DPLL output frequency offset, the PFD output is limited and the
DPLL output is frequency offset limited.
3.11.1
phase limit (refer to
by the MULTI_PH_APP bit.
3.11.2
Chapter 3.7.1.4 Hard Limit
hard limit is reached. This function, enabled by the T0_LIMT bit, will min-
imize the subsequent overshoot when T0 DPLL is pulling in.
3.11.3
clock with respect to the T0 DPLL output is measured. The device then
automatically accounts for the measured phase offset and compensates
an appropriate phase offset into the DPLL output so that the phase tran-
sients on the T0 DPLL output are minimized.
occurs:
put are minimized to be no more than 0.61 ns with PBO. The PBO can
also be frozen at the current phase offset by setting the PBO_FREZ bit.
When the PBO is frozen, the device will ignore any further PBO events
triggered by the above two conditions, and maintain the current phase
offset. When the PBO is disabled, there may be a phase shift on the T0
DPLL output and the T0 DPLL output tracks back to 0 degree phase off-
set with respect to the T0 selected input clock.
requirement specified in the Telcordia GR-1244-CORE is: ‘Input phase-
time changes of 3.5 µs or greater over an interval of less than 0.1 sec-
onds or less shall be built-out by stratum 2 and 3E clocks to reduce the
resulting clock phase-time change to less than 50 ns. Phase-time
changes of 1.0 µs or less over an interval of 0.1 seconds shall not be
built-out.’ Based on this requirement, phase-time changes of more than
Functional Description
IDT82V3380A
The DPLL output is locked to the selected input clock. According to
The PFD output is limited to be within ±1 UI or within the coarse
The DPLL output is limited to be within the DPLL hard limit (refer to
For T0 DPLL, the integral path value can be frozen when the DPLL
The PBO function is only supported by the T0 path.
When a PBO event is triggered, the phase offset of the selected input
A PBO event is triggered if any one of the following conditions
For the first two conditions, the phase transients on the T0 DPLL out-
The last condition is specially for stratum 2 and 3E clocks. The PBO
• T0 selected input clock switches (the PBO_EN bit is ‘1’);
• T0 DPLL exits from Holdover mode or Free-Run mode (the
• Phase-time changes on the T0 selected input clock are greater
PBO_EN bit is ‘1’);
than a programmable limit over an interval of less than 0.1 sec-
onds (the PH_MON_PBO_EN bit is ‘1’).
T0 / T4 DPLL OUTPUT
PFD OUTPUT LIMIT
FREQUENCY OFFSET LIMIT
PBO (T0 ONLY)
Chapter 3.7.1.2 Coarse Phase
Exceeding).
Loss), as determined
37
1.0 µs but less than 3.5 µs that occur over an interval of less than 0.1
seconds may or may not be built-out.
PH_MON_EN bit to monitor the phase-time changes on the T0 selected
input clock. When the phase-time changes are greater than a limit over
an interval of less than 0.1 seconds, a PBO event is triggered and the
phase transients on the DPLL output are absorbed. The limit is pro-
grammed by the PH_TR_MON_LIMT[3:0] bits, and can be calculated as
follows:
phase loss.
3.11.4
DPLL output can be adjusted. If the device is configured as the Master,
the PH_OFFSET_EN bit determines whether the input-to-output phase
offset is enabled; if the device is configured as the Slave, the input-to-
output phase offset is always enabled. If enabled, the input-to-output
phase offset can be adjusted by setting the PH_OFFSET[9:0] bits.
3.11.5
the T0 selected input clock and the T4 selected input clock respectively
every 125 µs period. Each DPLL has four output paths.
3.11.5.1
locking. The output can only be derived from the 77.76 MHz path or the
16E1/16T1 path. The output path is automatically selected and the out-
put is automatically divided to get the same frequency as the T0
selected input clock.
can be provided for the T4 DPLL input clock selection (refer to
Chapter 3.6 T0 / T4 DPLL Input Clock
cess.
An integrated Phase Transient Monitor can be enabled by the
The phase offset induced by PBO will never result in a coarse or fine
The phase offset of the T0 selected input clock with respect to the T0
The input-to-output phase offset can be calculated as follows:
The T0 DPLL output and the T4 DPLL output are phase aligned with
The four paths for T0 DPLL output are as follows:
T0 selected input clock is compared with a T0 DPLL output for DPLL
The T0 DPLL 77.76 MHz output or an 8 kHz signal derived from it
T0 DPLL outputs are provided for T0/T4 APLL or device output pro-
• 77.76 MHz path - outputs a 77.76 MHz clock;
• 16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by
• ETH/OBSAI/16E1/16T1 path - outputs a ETH, OBSAI, 16E1 or
• 12E1/24T1/E3/T3 path - outputs a 12E1, 24T1, E3 or T3 clock,
Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156
Phase Offset (ns) = PH_OFFSET[9:0] X 0.61
the IN_SONET_SDH bit;
16T1 clock, as selected by the T0_ETH_OBSAI_16E1_16T1_
SEL[1:0
as selected by the T0_12E1_24T1_E3_T3_SEL[1:0] bits.
PHASE OFFSET SELECTION (T0 ONLY)
FOUR PATHS OF T0 / T4 DPLL OUTPUTS
T0 Path
]
bits;
SYNCHRONOUS ETHERNET WAN PLL™
Selection).
May 16, 2011