IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 84

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

IN4_CNFG - Input Clock 4 Configuration
Programming Information
IDT82V3380A
Address: 17H
Type: Read / Write
Default Value: 00000000
DIRECT_DIV
5 - 4
3 - 0
Bit
7
6
7
BUCKET_SEL[1:0]
IN_FREQ[3:0]
DIRECT_DIV
LOCK_8K
Name
LOCK_8K
6
Refer to the description of the LOCK_8K bit (b6, 17H).
This bit, together with the DIRECT_DIV bit (b7, 17H), determines whether the DivN Divider or the Lock 8k Divider is used for
IN4:
These bits select one of the four groups of leaky bucket configuration registers for IN4:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN4:
0000: 8 kHz. (default)
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz.
0100: 25.92 MHz.
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For the IN4, the required frequency should not be set higher than that of the input clock.
BUCKET_SEL1
DIRECT_DIV bit
5
0
0
1
1
BUCKET_SEL0
4
LOCK_8K bit
0
1
0
1
84
IN_FREQ3
3
Description
IN_FREQ2
Both bypassed (default)
2
SYNCHRONOUS ETHERNET WAN PLL™
Lock 8k Divider
Used Divider
DivN Divider
Reserved
IN_FREQ1
1
IN_FREQ0
May 16, 2011
0