IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 34

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

3.10
without being affected by operating conditions or silicon process varia-
tions. It integrates a PFD (Phase & Frequency Detector), a LPF (Low
Pass Filter) and a DCO (Digital Controlled Oscillator), which forms a
closed loop. If no input clock is selected, the loop is not closed, and the
PFD and LPF do not function.
phase loss and fine phase loss (refer to
Chapter 3.7.1.3 Fine Phase
T4 DPLL feedback with respect to the selected input clock is indicated
by the CURRENT_PH_DATA[15:0] bits. It can be calculated as follows:
grammable. A range of bandwidths and damping factors can be set to
meet different application requirements. Generally, the lower the damp-
ing factor is, the longer the locking time is and the more the gain is.
put is always multiplied on the basis of the master clock. The phase and
frequency offset of the DPLL output may be locked to those of the
selected input clock. The current frequency offset with respect to the
master clock is indicated by the CURRENT_DPLL_FREQ[23:0] bits, and
can be calculated as follows:
3.10.1
mode.
used depending on DPLL locking stages: starting, acquisition and
locked.
selected input clock, the starting bandwidth and damping factor are
used. They are set by the T0_DPLL_START_BW[4:0] bits and the
T0_DPLL_START_DAMPING[2:0] bits respectively.
are used. They are set by the T0_DPLL_ACQ_BW[4:0] bits and the
T0_DPLL_ACQ_DAMPING[2:0] bits respectively.
and
T0_DPLL_LOCKED_BW[4:0]
T0_DPLL_LOCKED_DAMPING[2:0] bits respectively.
T0 DPLL operates in different DPLL locking stages: starting, acquisition
and locked, as controlled by the device automatically.
less of the T0 DPLL locking stage, as controlled by the AUTO_BW_SEL
bit.
Functional Description
IDT82V3380A
The T0/T4 DPLL gives a stable performance in different applications
The PFD detects the phase error, including the fast loss, coarse
The LPF filters jitters. Its 3 dB bandwidth and damping factor are pro-
The DCO controls the DPLL output. The frequency of the DPLL out-
The T0 DPLL loop is closed except in Free-Run mode and Holdover
For a closed loop, different bandwidths and damping factors can be
In the first two seconds when the T0 DPLL attempts to lock to the
During the acquisition, the acquisition bandwidth and damping factor
When the T0 selected input clock is locked, the locked bandwidth
The corresponding bandwidth and damping factor are used when the
Only the locked bandwidth and damping factor can be used regard-
damping
Averaged Phase Error (ns) = CURRENT_PH_DATA[15:0] X 0.61
Current Frequency Offset (ppm) = CURRENT_DPLL_FREQ[23:0] X
0.000011
T0 / T4 DPLL OPERATING MODE
T0 DPLL OPERATING MODE
factor
are
Loss). The averaged phase error of the T0/
used.
bits
Chapter 3.7.1.1 Fast Loss
They
are
and
set
by
the
the
to
34
3.10.1.1
and is not affected by any input clock. The accuracy of the T0 DPLL out-
put is equal to that of the master clock.
3.10.1.2
selected input clock.
3.10.1.3
and frequency offset of the T0 DPLL output track those of the T0
selected input clock.
the FAST_LOS_SW bit is ‘1’, the T0 DPLL is unlocked (refer to
Chapter 3.7.1.1 Fast
operating mode is switched automatically; if the T0 selected input clock
is in fast loss status and the FAST_LOS_SW bit is ‘0’, the T0 DPLL lock-
ing status is not affected and the T0 DPLL will enter Temp-Holdover
mode automatically.
3.10.1.3.1 Temp-Holdover Mode
selected input clock switch or no qualified input clock available when the
operating mode switch is under external control.
selected input clock. The T0 DPLL operation in Temp-Holdover mode
and that in Holdover mode are alike (refer to
Mode) except the frequency offset acquiring methods. See
Chapter 3.10.1.5 Holdover Mode
method is selected by the TEMP_HOLDOVER_MODE[1:0] bits, as
shown in
Table 19: Frequency Offset Control in Temp-Holdover Mode
Holdover mode.
3.10.1.4
selected input clock.
3.10.1.5
acquired in Locked mode to control its output. The T0 DPLL output is not
phase locked to any input clock. The frequency offset acquiring method
TEMP_HOLDOVER_MODE[1:0]
In Free-Run mode, the T0 DPLL output refers to the master clock
In Pre-Locked mode, the T0 DPLL output attempts to track the
The Pre-Locked mode is a secondary, temporary mode.
In Locked mode, the T0 selected input clock is locked. The phase
In this mode, if the T0 selected input clock is in fast loss status and
The T0 DPLL will automatically enter Temp-Holdover mode with a
In Temp-Holdover mode, the T0 DPLL has temporarily lost the
The device automatically controls the T0 DPLL to exit from Temp-
In Lost-Phase mode, the T0 DPLL output attempts to track the
The Lost-Phase mode is a secondary, temporary mode.
In Holdover mode, the T0 DPLL resorts to the stored frequency data
Table
Free-Run Mode
Pre-Locked Mode
Locked Mode
Lost-Phase Mode
Holdover Mode
00
01
10
11
19:
Loss) and will enter Lost-Phase mode when the
SYNCHRONOUS ETHERNET WAN PLL™
the same as that used in Holdover mode
Frequency Offset Acquiring Method
for details about the methods. The
Automatic Slow Averaged
Automatic Fast Averaged
Automatic Instantaneous
Chapter 3.10.1.5 Holdover
May 16, 2011