IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 24

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

Table 6: Related Bit / Register in Chapter 3.5
3.5.3
ence clock. The reference clock can be derived from the master clock or
the output of T0 DPLL, as determined by the FREQ_MON_CLK bit.
the FREQ_MON_HARD_EN bit is ‘1’, a frequency hard alarm is raised
when the frequency of the input clock with respect to the reference clock
is above the threshold; the alarm is cleared when the frequency is below
the threshold.
status of the input clock is indicated by the INn_FREQ_HARD_ALARM
bit (14 ≥ n ≥ 1). When the FREQ_MON_HARD_EN bit is ‘0’, no fre-
quency hard alarm is raised even if the input clock is above the fre-
quency hard alarm threshold.
Functional Description
IDT82V3380A
Frequency is monitored by comparing the input clock with a refer-
A frequency hard alarm threshold is set for frequency monitoring. If
The frequency hard alarm threshold can be calculated as follows:
If the FREQ_MON_HARD_EN bit is ‘1’, the frequency hard alarm
LOWER_THRESHOLD_n_DATA[7:0] (3 ≥ n ≥ 0)
UPPER_THRESHOLD_n_DATA[7:0] (3 ≥ n ≥ 0)
INn_NO_ACTIVITY_ALARM (14 ≥ n ≥ 1)
Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_
THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0]
BUCKET_SIZE_n_DATA[7:0] (3 ≥ n ≥ 0)
INn_FREQ_HARD_ALARM (14 ≥ n ≥ 1)
DECAY_RATE_n_DATA[1:0] (3 ≥ n ≥ 0)
ALL_FREQ_HARD_THRESHOLD[3:0]
FREQUENCY MONITORING
FREQ_MON_FACTOR[3:0]
IN_FREQ_READ_CH[3:0]
FREQ_MON_HARD_EN
IN_FREQ_VALUE[7:0]
IN_NOISE_WINDOW
BUCKET_SEL[1:0]
FREQ_MON_CLK
AMI1_LOS
AMI2_LOS
AMI1_LOS
AMI2_LOS
Bit
1
1
2
2
LOWER_THRESHOLD_0_CNFG ~ LOWER_THRESHOLD_3_CNFG
UPPER_THRESHOLD_0_CNFG ~ UPPER_THRESHOLD_3_CNFG
BUCKET_SIZE_0_CNFG ~ BUCKET_SIZE_3_CNFG
DECAY_RATE_0_CNFG ~ DECAY_RATE_3_CNFG
ALL_FREQ_MON_THRESHOLD_CNFG
INTERRUPTS3_ENABLE_CNFG
IN1_IN2_STS ~ IN13_IN14_STS
24
FREQ_MON_FACTOR_CNFG
IN_FREQ_READ_CH_CNFG
PHASE_MON_PBO_CNFG
IN1_CNFG ~ IN14_CNFG
MON_SW_PBO_CNFG
selection for T0/T4 DPLL.
with respect to the reference clock are monitored. If any edge drifts out-
side ±5%, the input clock is disqualified for clock selection for T0/T4
DPLL. The input clock is qualified if any edge drifts inside ±5%. This
function is supported only when the IN_NOISE_WINDOW bit is ‘1’.
can be read by doing the following step by step:
depends on the application.
IN_FREQ_READ_STS
INTERRUPTS3_STS
The input clock with a frequency hard alarm is disqualified for clock
In addition, if the input clock is 2 kHz, 4 kHz or 8 kHz, its clock edges
The frequency of each input clock with respect to the reference clock
Note that the value set by the FREQ_MON_FACTOR[3:0] bits
1. Select an input clock by setting the IN_FREQ_READ_CH[3:0]
2. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate
Register
as follows:
bits;
Input Clock Frequency (ppm) = IN_FREQ_VALUE[7:0] X
FREQ_MON_FACTOR[3:0]
SYNCHRONOUS ETHERNET WAN PLL™
14 ~ 17, 19 ~ 22
Address (Hex)
33, 37, 3B, 3F
31, 35, 39, 3D
32, 36, 3A, 3E
34, 38, 3C, 40
43 ~ 49
May 16, 2011
0B
2F
2E
0F
12
78
41
42