IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 143

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

OUT5_FREQ_CNFG - Output Clock 5 Frequency Configuration
Programming Information
IDT82V3380A
Address: 6FH
Type: Read / Write
Default Value: 00000100
OUT5_PATH_S
7 - 4
3 - 0
Bit
EL3
7
OUT5_PATH_SEL[3:0]
OUT5_DIVIDER[3:0]
OUT5_PATH_S
Name
EL2
6
These bits select an input to OUT5.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
0111: The output of T0 DPLL ETH/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
These bits select a division factor of the divider for OUT5.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
(selected by the OUT5_PATH_SEL[3:0] bits (b7~4, 6FH)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to
Table 26~Table 28
OUT5_PATH_S
EL1
5
Table 25
for the division factor selection.
OUT5_PATH_S
for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
EL0
4
143
OUT5_DIVIDER
3
3
Description
OUT5_DIVIDER
2
2
SYNCHRONOUS ETHERNET WAN PLL™
OUT5_DIVIDER
1
1
OUT5_DIVIDER
May 16, 2011
0
0