IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 16

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

Pin Description
IDT82V3380A
Table 1: Pin Description (Continued)
ALE / SCLK
AD0 / SDO
A1 / CLKE
A0 / SDI
Name
AD1
AD2
AD3
AD4
AD5
AD6
AD7
WR
RD
A2
A3
A4
A5
A6
Pin No.
69
68
67
66
65
64
63
83
82
81
80
79
78
77
76
71
72
73
pull-down
pull-down
pull-down
pull-up
pull-up
I/O
I/O
I/O
I
I
I
CMOS
CMOS
CMOS
CMOS
CMOS
Type
A[6:0]: Address Bus
In EPROM mode, these pins are outputs. They are the address bus of the EPROM interface.
Intel and Motorola modes, these pins are inputs, they are the address bus of the microprocessor
interface.
SDI: Serial Data Input
In Serial mode, this pin is used as the serial data input. Address and data on this pin are serially
clocked into the device on the rising edge of SCLK.
CLKE: SCLK Active Edge Selection
In Serial mode, this pin is an input, it selects the active edge of SCLK to update the SDO:
High - The falling edge;
Low - The rising edge.
In Multiplexed mode, A0/SDI, A1/CLKE and A[6:2] pins should be connected to ground.
In Serial mode, A[6:2] pins should be connected to ground.
See Table 35 for details.
AD[7:0]: Address / Data Bus
In EPROM, Intel and Motorola modes, these pins are the bi-directional data bus of the micropro-
cessor interface.
In Multiplexed mode, these pins are the bi-directional address/data bus of the microprocessor
interface.
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked out of
the device on the active edge of SCLK.
In Serial mode, AD[7:1] pins should be connected to ground.
WR: Write Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a write operation.
In Motorola mode, this pin is asserted low to initiate a write operation or s asserted high to initiate
a read operation.
In EPROM and Serial modes, this pin should be connected to ground.
RD: Read Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a read operation.
In EPROM, Motorola and Serial modes, this pin should be connected to ground.
ALE: Address Latch Enable
In Multiplexed mode, the address on AD[7:0] pins is sampled into the device on the falling edge of
ALE.
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated on the
active edge of SCLK. The active edge is determined by the CLKE.
In EPROM, Intel and Motorola modes, this pin should be connected to ground.
16
Description
SYNCHRONOUS ETHERNET WAN PLL™
1
May 16, 2011