IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 120

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

REMOTE_INPUT_VALID2_CNFG - Input Clocks Validity Configuration 2
PRIORITY_TABLE1_STS - Priority Status 1 *
Programming Information
IDT82V3380A
Address: 4DH
Type: Read / Write
Default Value: XX111111
Address: 4EH
Type: Read
Default Value: 00000000
ORITY_VALIDA
HIGHEST_PRI
7 - 6
5 - 0
7 - 4
3 - 0
Bit
Bit
TED3
7
7
-
HIGHEST_PRIORITY_VALIDATED[3:0]
CURRENTLY_SELECTED_INPUT[3:0]
INn_VALID
Name
ORITY_VALIDA
HIGHEST_PRI
-
TED2
6
6
-
Name
Reserved.
This bit controls whether the corresponding INn is allowed to be locked for automatic selection. Here n is any one of 14 to 9.
0: Enabled.
1: Disabled. (default)
ORITY_VALIDA
HIGHEST_PRI
IN14_VALID
TED1
5
5
These bits indicate a qualified input clock with the highest priority.
0000: No input clock is qualified. (default)
0001: IN1.
0010: IN2.
......
1101: IN13.
1110: IN14.
1111: Reserved.
Note that the input clock is indicated by these bits only when the corresponding INn (b7-0, 4CH) or INn
(b5-0, 4DH) bit is ‘0’.
These bits indicate the T0/T4 selected input clock.
0000: No input clock is selected; or the T4 selected input clock is the T0 DPLL output. (default)
0001: IN1 is selected.
0010: IN2 is selected.
......
1101: IN13 is selected.
1110: IN14 is selected.
1111: Reserved.
Note that the input clock is indicated by these bits only when the corresponding INn (b7-0, 4CH) or INn
(b5-0, 4DH) bit is ‘0’.
ORITY_VALIDA
HIGHEST_PRI
IN13_VALID
TED0
4
4
120
CURRENTLY_S
ELECTED_INP
IN12_VALID
UT3
3
3
Description
CURRENTLY_S
ELECTED_INP
Description
IN11_VALID
UT2
2
2
SYNCHRONOUS ETHERNET WAN PLL™
CURRENTLY_S
ELECTED_INP
IN10_VALID
UT1
1
1
CURRENTLY_S
ELECTED_INP
IN9_VALID
May 16, 2011
UT0
0
0