IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 22

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

Table 4: Pre-Divider Function
Table 5: Related Bit / Register in Chapter 3.4
Functional Description
Note 1: Please see register description for details.
Note 2: For 156.25 MHz, 312.5 MHz and 625 MHz differential input clock frequency, the divider mode should be DivN with IN_FREQ[3:0] = ‘1100’: 6.25 MHz.
IDT82V3380A
Divider Bypassed
Lock 8K Divider
HF- Divider
Pre-Divider
DivN
PRE_DIV_CH_VALUE[3:0]
PRE_DIVN_VALUE[14:0]
IN_2K_4K_8K_INV
2
IN_FREQ[3:0]
DIRECT_DIV
IN5_DIV[1:0]
IN6_DIV[1:0]
LOCK_8K
Bit
Example:
2KHz, 4KHz, 8KHz, 1.544 MHz, 2.048 MHz,
6.48 MHz, 19.44 MHz, 25.92 MHz or 38.88
1.544 MHz, 2.048 MHz, 6.48 MHz, 19.44
MHz, 25.92 MHz or 38.88 MHz
Input Clock INn frequency
25 MHz = 3125 x 8 kHz
(2 ≤ N ≤ 19440)
>155.52 MHz
Nx8kHz
MHz
PRE_DIVN[14:8]_CNFG, PRE_DIVN[7:0]_CNFG
Example:
LOCK_8K= 1’b; DIRECT_DIV= 0’b (select Lock 8k Divider)
IN_FREQ[3:0] – set to match input Clock INn frequency.
IN_FREQ[3:0] – set to match input Clock INn frequency.
LOCK_8K= 0’b; DIRECT_DIV= 1’b (select DivN Divider)
LOCK_8K= 0’b; DIRECT_DIV= 0’b (Bypass Dividers)
IN_FREQ[3:0] – set to the DPLL required frequency.
Division Factor = 3125 -1= 3124 Dec (or 0C34h)
IN1_CNFG ~ IN14_CNFG
IN3_CNFG ~ IN14_CNFG
IN5_IN6_HF_DIV_CNFG
22
FR_MFR_SYNC_CNFG
PRE_DIV_CH_CNFG
PRE_DIVN_VALUE[14:8]= 0Ch
PRE_DIVN_VALUE[7:0]= 34h
PRE_DIV_CH_VALUE[3:0]
PRE_DIVN_VALUE[14:0]
(‘0000’: 8 kHz (default))
25 MHz = 3125 x 8kHz
Register
Control Register
IN5_DIV[1:0]
IN6_DIV[1:0]
SYNCHRONOUS ETHERNET WAN PLL™
IN5_IN6_HF_DIV_CNFG (18)
PRE_DIVN[14:8]_CNFG (25),
PRE_DIVN[7:0]_CNFG (24)
PRE_DIV_CH_CNFG (23)
IN3_CNFG ~ IN14_CNFG
IN3_CNFG ~ IN14_CNFG
IN3_CNFG ~ IN14_CNFG
Register/ Address
(16 ~ 17, 19 ~ 22)
(16 ~ 17, 19 ~ 22)
(16 ~ 17, 19 ~ 22)
14 ~ 17, 19 ~ 22
Address (Hex)
16, 17, 19 ~ 22
May 16, 2011
25, 24
18
74
23
1