IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 137

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2
CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1 *
CURRENT_DPLL_PHASE[15:8]_STS - DPLL Current Phase Status 2 *
Programming Information
Address: 68H
Type: Read
Default Value: 00000000
IDT82V3380A
Address: 67H
Type: Read / Write
Default Value: 00011001
Address: 69H
Type: Read
Default Value: 00000000
CURRENT_PH
DPLL_FREQ_H
CURRENT_PH
ARD_LIMT15
7 - 0
7 - 0
_DATA15
7 - 0
_DATA7
Bit
Bit
Bit
7
7
7
DPLL_FREQ_HARD_LIMT[15:8]
CURRENT_PH_DATA[15:8]
CURRENT_PH_DATA[7:0] Refer to the description of the CURRENT_PH_DATA[15:8] bits (b7~0, 69H).
CURRENT_PH
DPLL_FREQ_H
CURRENT_PH
ARD_LIMT14
_DATA14
_DATA6
Name
Name
6
6
6
Name
CURRENT_PH
CURRENT_PH
DPLL_FREQ_H
ARD_LIMT13
_DATA13
_DATA5
The CURRENT_PH_DATA[15:0] bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the
averaged phase error of the T0/T4 DPLL feedback with respect to the selected input clock in ns will be gotten.
5
5
5
The DPLL_FREQ_HARD_LIMT[15:0] bits represent an unsigned integer. If the value is multiplied by 0.0014, the
DPLL hard limit for T0 and T4 paths in ppm will be gotten.
The DPLL hard limit is symmetrical about zero.
CURRENT_PH
CURRENT_PH
DPLL_FREQ_H
ARD_LIMT12
_DATA12
_DATA4
4
4
4
137
CURRENT_PH
CURRENT_PH
DPLL_FREQ_H
ARD_LIMT11
_DATA11
_DATA3
3
3
3
Description
Description
Description
CURRENT_PH
CURRENT_PH
DPLL_FREQ_H
ARD_LIMT10
_DATA10
_DATA2
2
2
2
SYNCHRONOUS ETHERNET WAN PLL™
CURRENT_PH
DPLL_FREQ_H
CURRENT_PH
ARD_LIMT9
_DATA1
_DATA9
1
1
1
CURRENT_PH
DPLL_FREQ_H
CURRENT_PH
ARD_LIMT8
_DATA0
May 16, 2011
_DATA8
0
0
0