IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 27

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

3.7
Chapter 3.5 Input Clock Quality
is always monitored.
3.7.1
3.7.1.1
secutive clock cycles. It is cleared once an active clock edge is detected.
unlocked if the FAST_LOS_SW bit is ‘1’. For T4 path, the occurrence of
the fast loss will result in T4 DPLL unlocked regardless of the
FAST_LOS_SW bit.
3.7.1.2
back signal. If the phase-compared result exceeds the coarse phase
limit, a coarse phase loss is triggered. It is cleared once the phase-com-
pared result is within the coarse phase limit.
phase limit depends on the MULTI_PH_8K_4K_2K_EN bit, the
WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to
Table
kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN
bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to
unlocked if the COARSE_PH_LOS_LIMT_EN bit is ‘1’.
Functional Description
Table 11: Coarse Phase Limit Programming (the selected input
clock of 2 kHz, 4 kHz or 8 kHz)
Table 12: Coarse Phase Limit Programming (the selected input
clock of other than 2 kHz, 4 kHz and 8 kHz)
IDT82V3380A
MULTI_PH_8K_4K
The quality of the selected input clock is always monitored (refer to
The following events is always monitored:
A fast loss is triggered when the selected input clock misses 2 con-
For T0 path, the occurrence of the fast loss will result in T0 DPLL
The T0/T4 DPLL compares the selected input clock with the feed-
When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse
The occurrence of the coarse phase loss will result in T0/T4 DPLL
• Fast Loss;
• Coarse Phase Loss;
• Fine Phase Loss;
• Hard Limit Exceeding.
11. When the selected input clock is of other frequencies but 2
_2K_EN
WIDE_EN
0
1
0
1
SELECTED INPUT CLOCK MONITORING
T0 / T4 DPLL LOCKING DETECTION
Fast Loss
Coarse Phase Loss
WIDE_EN
don’t-care
0
1
set by the PH_LOS_COARSE_LIMT[3:0] bits
set by the PH_LOS_COARSE_LIMT[3:0] bits
Monitoring) and the DPLL locking status
Coarse Phase Limit
Coarse Phase Limit
±1 UI
±1 UI
±1 UI
Table
12.
27
3.7.1.3
back signal. If the phase-compared result exceeds the fine phase limit
programmed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is
triggered. It is cleared once the phase-compared result is within the fine
phase limit.
unlocked if the FINE_PH_LOS_LIMT_EN bit is ‘1’.
3.7.1.4
and DPLL hard limit. When the frequency of the DPLL output with
respect to the master clock exceeds the DPLL soft / hard limit, a DPLL
soft / hard alarm will be raised; the alarm is cleared once the frequency
is within the corresponding limit. The occurrence of the DPLL soft alarm
does not affect the T0/T4 DPLL locking status. The DPLL soft alarm is
indicated by the corresponding T0_DPLL_SOFT_FREQ_ALARM /
T4_DPLL_SOFT_FREQ_ALARM bit. The occurrence of the DPLL hard
alarm will result in T0/T4 DPLL unlocked if the FREQ_LIMT_PH_LOS bit
is ‘1’.
and can be calculated as follows:
bits and can be calculated as follows:
3.7.2
The DPLL is in locked state if none of the following events is triggered
during 2 seconds; otherwise, the DPLL is unlocked.
FINE_PH_LOS_LIMT_EN bit or the FREQ_LIMT_PH_LOS bit is ‘0’, the
DPLL locking status will not be affected even if the corresponding event
is triggered. If all these bits are ‘0’, the DPLL will be in locked state in 2
seconds.
T4_DPLL_LOCK bit.
changes (from ‘lock’ to ‘unlock’ or from ‘unlock’ to ‘lock’). If the T4_STS
bit is ‘1’, an interrupt will be generated.
The T0/T4 DPLL compares the selected input clock with the feed-
The occurrence of the fine phase loss will result in T0/T4 DPLL
Two limits are available for this monitoring. They are DPLL soft limit
The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits
The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0]
The DPLL locking status depends on the locking monitoring results.
If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the
The DPLL locking status is indicated by the T0_DPLL_LOCK /
The T4_STS
• Fast Loss (the FAST_LOS_SW bit is ‘1’);
• Coarse Phase Loss (the COARSE_PH_LOS_LIMT_EN bit is
• Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is ‘1’);
• DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is ‘1’).
DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724
DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014
‘1’);
Fine Phase Loss
Hard Limit Exceeding
LOCKING STATUS
1
bit will be set when the locking status of the T4 DPLL
SYNCHRONOUS ETHERNET WAN PLL™
May 16, 2011
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