IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 153

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

8.4
the electrical performance, a land pattern must be incorporated on the
Printed Circuit Board (PCB) within the footprint of the package corre-
sponding to the exposed metal pad or exposed heat slug on the pack-
age, as shown in
and electrical grounding from the package to the board through a solder
joint, thermal vias are necessary to effectively conduct from the surface
of the PCB to the ground plane(s). The land pattern must be connected
to ground through these vias. The vias act as ‘heat pipes’. The number
of vias (i.e. ‘heat pipes’) are application specific and dependent upon the
package power dissipation as well as electrical conductivity require-
ments. Thus, thermal and electrical analysis and/or testing are recom-
mended to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is incorpo-
rated in the land pattern. It is recommended to use as many vias con-
Thermal Management
IDT82V3380A
In order to maximize both the removal of heat from the package and
While the land pattern on the PCB provides a means of heat transfer
TQFP EPAD THERMAL RELEASE PATH
Figure
29. The solderable area on the PCB, as defined
SOLDER
Figure 29. Assembly for Expose Pad thermal Release Path (Side View)
PAD
PIN
PIN
GROUND
PLANE
EXPOSED HEAT SLUG
THERMAL
VIA
153
by the solder mask, should be at least the same size/shape as the
exposed pad/slug area on the package to maximize the thermal/electri-
cal performance. Sufficient clearance should be designed on the PCB
between the outer edges of the land pattern and the inner edges of pad
pattern for the leads to avoid any shorts.
nected to ground as possible. It is also recommended that the via
diameter should be 12 to 13mils (0.30 to 0.33mm) with 1 oz copper via
barrel plating. This is desirable to avoid any solder wicking inside the via
during the soldering process which may result in voids in solder between
the exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a guide-
line only. For further information, please refer to the Application Note on
the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance
Leadframe Base Package, Amkor Technology.
(GROUND PAD)
PATTERN
SOLDER
LAND
SYNCHRONOUS ETHERNET WAN PLL™
PIN
PIN
PAD
SOLDER
May 16, 2011