IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 44

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

Table 30: Synchronization Control
3.13.2
FRSYNC_8K and MFRSYNC_2K pins if enabled by the 8K_EN and
2K_EN bits respectively. They are CMOS outputs.
are aligned with the output clock. They can be synchronized to the frame
sync input signal.
clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an external
sync alarm will be raised and EX_SYNC1 is disabled to synchronize the
frame sync output signals. The external sync alarm is cleared once
EX_SYNC1 with respect to the T0 selected input clock is within the limit.
If it is within the limit, whether EX_SYNC1 is enabled to synchronize the
frame sync output signal is determined by the AUTO_EXT_SYNC_EN
bit and the EXT_SYNC_EN bit. Refer to
frame sync output signal, it should be adjusted to align itself with the T0
selected input clock. Nominally, the falling edge of EX_SYNC1 is aligned
with the rising edge of the T0 selected input clock. EX_SYNC1 may be
0.5 UI early/late or 1 UI late due to the circuit and board wiring delays.
Setting the sampling of EX_SYNC1 by the SYNC_PH1[1:0] bits will
compensate this early/late. Refer to
Functional Description
IDT82V3380A
AUTO_EXT_SYNC_EN EXT_SYNC_EN
Figure 9. On Target Frame Sync Input Signal Timing
An 8 kHz and a 2 kHz frame sync signals are output on the
The two frame sync signals are derived from the T0 APLL output and
If the frame sync input signal with respect to the T0 selected input
When the frame sync input signal is enabled to synchronize the
output signals
Output clocks
EX_SYNC1
Frame sync
T0 selected
input clock
don’t-care
0
1
FRAME SYNC OUTPUT SIGNALS
0
1
1
Figure 9
Table 30
to
Figure
for details.
12.
Enabled if the T0 selected input clock is IN11; otherwise, disabled.
44
external sync alarm status. The external sync alarm is indicated by the
EX_SYNC_ALARM
rence of the external sync alarm will trigger an interrupt.
by setting the 8K_INV and 2K_INV bits respectively. The frame sync out-
puts can be 50:50 duty cycle or pulsed, as determined by the 8K_PUL
and 2K_PUL bits respectively. When they are pulsed, the pulse width is
defined by the period of OUT3; and they are pulsed on the position of
the falling or rising edge of the standard 50:50 duty cycle, as selected by
the 2K_8K_PUL_POSITION bit.
tive, 1UI late EX_SYNC1 shall be set. 2K pulse is output by writing
‘0x71’ to the FR_MFR_SYNC_CNFG register (74H); 8K pulse is output
by writing ‘0x6C’ to the FR_MFR_SYNC_CNFG register. When the
pulse is negative, on target EX_SYNC1 shall be set. 2K pulse is output
by writing ‘0x73’ to the FR_MFR_SYNC_CNFG register; 8K pulse is out-
put by writing ‘0x64’ to the FR_MFR_SYNC_CNFG register. To align
EX_SYNC1 with Frame sync output signals, the pulse width only can be
38.88 MHz, 19.44 MHz and 6.48 MHz for master/slave application.
Refer to
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing
The EX_SYNC_ALARM_MON bit indicates whether EX_SYNC1 is in
The 8 kHz and the 2 kHz frame sync output signals can be inverted
2K/8K pulse mode can also be supported. When the pulse is posi-
output signals
Output clocks
EX_SYNC1
Frame sync
T0 selected
input clock
Figure 13
Synchronization
Disabled
Enabled
and
1
bit. If the EX_SYNC_ALARM
Figure
SYNCHRONOUS ETHERNET WAN PLL™
14.
2
bit is ‘1’, the occur-
May 16, 2011