IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 149

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

7.2.9
PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration
PHASE_OFFSET[7:0]_CNFG - Phase Offset Configuration 1
Programming Information
IDT82V3380A
Address:78H
Type: Read / Write
Default Value: 0X000110
Address:7AH
Type: Read / Write
Default Value: 00000000
IN_NOISE_WIN
PH_OFFSET7
3 - 0
7 - 0
Bit
Bit
7
6
5
4
DOW
7
7
PBO & PHASE OFFSET CONTROL REGISTERS
PH_TR_MON_LIMT[3:0]
PH_OFFSET[7:0] Refer to the description of the PH_OFFSET[9:8] bits (b1~0, 7BH).
IN_NOISE_WINDOW
PH_MON_PBO_EN
PH_MON_EN
PH_OFFSET6
Name
Name
-
6
-
6
PH_MON_EN
This bit determines whether the input clock whose edge respect to the reference clock is outside ±5% is enabled to be
selected for T0/T4 DPLL.
0: Disabled. (default)
1: Enabled.
Reserved.
This bit is valid only when the PH_MON_PBO_EN bit (b4, 78H) is ‘1’. It determines whether the Phase Transient Monitor
is enabled to monitor the phase-time changes on the T0 selected input clock.
0: Disabled. (default)
1: Enabled.
This bit determines whether a PBO event is triggered when the phase-time changes on the T0 selected input clock are
greater than a programmable limit over an interval of less than 0.1 seconds with the PH_MON_EN bit being ‘1’. The limit
is programmed by the PH_TR_MON_LIMT[3:0] bits (b3~0, 78H).
0: Disabled. (default)
1: Enabled.
These bits represent an unsigned integer. The Phase Transient Monitor limit in ns can be calculated as follows:
Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156.
PH_OFFSET5
5
5
PH_MON_PBO
PH_OFFSET4
_EN
4
4
149
PH_TR_MON_L
PH_OFFSET3
IMT3
3
3
Description
Description
PH_TR_MON_L
PH_OFFSET2
IMT2
2
2
SYNCHRONOUS ETHERNET WAN PLL™
PH_TR_MON_L
PH_OFFSET1
IMT1
1
1
PH_TR_MON_L
PH_OFFSET0
May 16, 2011
IMT0
0
0