IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 96

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

PRE_DIV_CH_CNFG - DivN Divider Channel Selection
PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1
Programming Information
IDT82V3380A
Address: 23H
Type: Read / Write
Default Value: XXXX0000
Address: 24H
Type: Read / Write
Default Value: 00000000
PRE_DIVN_VA
7 - 4
3 - 0
7 - 0
7
-
Bit
Bit
LUE7
7
PRE_DIV_CH_VALUE[3:0]
PRE_DIVN_VALUE[7:0] Refer to the description of the PRE_DIVN_VALUE[14:8] bits (b6~0, 25H).
6
-
PRE_DIVN_VA
Name
Name
LUE6
-
6
5
-
4
-
PRE_DIVN_VA
Reserved.
This register is an indirect address register for Register 24H and 25H.
These bits select an input clock. The value set in the PRE_DIVN_VALUE[14:0] bits (25H, 24H) is available for the
selected input clock.
0000: Reserved. (default)
0001, 0010: Reserved.
0011: IN3.
0100: IN4.
......
1101: IN13.
1110: IN14.
1111: Reserved.
LUE5
5
PRE_DIV_CH_VALUE3
3
PRE_DIVN_VA
LUE4
4
96
PRE_DIV_CH_VALUE2
PRE_DIVN_VA
LUE3
3
2
Description
Description
PRE_DIVN_VA
PRE_DIV_CH_VALUE1
LUE2
SYNCHRONOUS ETHERNET WAN PLL™
2
1
PRE_DIVN_VA
LUE1
1
PRE_DIV_CH_VALUE0
PRE_DIVN_VA
May 16, 2011
0
LUE0
0