IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 10

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

DESCRIPTION
chronous Equipment Timing Source for Stratum 2, 3E, 3, SMC, 4E and 4
clocks in SONET / SDH equipments, DWDM and Wireless base station,
such as GSM, 3G, DSL concentrator, Router and Access Network appli-
cations.
clock from STM-N or OC-n, PDH network synchronization timing and
external synchronization reference timing.
sists of T0 and T4 paths. The T0 path is a high quality and highly config-
urable path to provide system clock for node timing synchronization
within a SONET / SDH network. The T4 path is simpler and less configu-
rable for equipment synchronization. The T4 path locks independently
from the T0 path or locks to the T0 path.
each for DPLL locking. Both the T0 and T4 paths support three primary
operating modes: Free-Run, Locked and Holdover. In Free-Run mode,
the DPLL refers to the master clock. In Locked mode, the DPLL locks to
the selected input clock. In Holdover mode, the DPLL resorts to the fre-
Description
IDT82V3380A
The IDT82V3380A is an integrated, single-chip solution for the Syn-
The device supports three types of input clock sources: recovered
Based on ITU-T G.783 and Telcordia GR-253-CORE, the device con-
An input clock is automatically or manually selected for T0 and T4
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quency data acquired in Locked mode. Whatever the operating mode is,
the DPLL gives a stable performance without being affected by operat-
ing conditions or silicon process variations.
device will be in a better jitter/wander performance.
560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different
settings cover all SONET / SDH clock synchronization requirements.
cations. The master clock is used as a reference clock for all the internal
circuits in the device. It can be calibrated within ±741 ppm.
interface. The device supports five microprocessor interface modes:
EPROM, Multiplexed, Intel, Motorola and Serial.
this application, two devices should be used together to enable system
protection against single chip failure. See
for details.
If the DPLL outputs are processed by T0/T4 APLL, the outputs of the
The device provides programmable DPLL bandwidths: 0.5 mHz to
A high stable input is required for the master clock in different appli-
All the read/write registers are accessed through a microprocessor
In general, the device can be used in Master/Slave application. In
SYNCHRONOUS ETHERNET IDT WAN PLL™
Chapter 4 Typical Application
May 16, 2011