IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 43

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

Table 29: Outputs on OUT8 & OUT9
Functional Description
Table 28: Outputs on OUT3 & OUT7 if Derived from T4 APLL
IDT82V3380A
OUT8_EN / OUT9_EN T4_INPUT_FAIL
Note:
1. n = 3 or 7. Each output is assigned a frequency divider.
2. In the APLL, the selected T0/T4 DPLL output may be multiplied. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is
reserved.
3. The 622.08 MHz and 311.04 MHz differential signals are only output on OUT7.
4. OUT7 doesn’t support 25MHz or 125MHz when non-ethernet clock signals are selected for OUT3.
OUTn_DIVIDER[3
:0] (Output
Divider)
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
0
1
1
77.76 MHz X 4 12E1 X 4 16E1 X 4 24T1 X 4 16T1 X 4
622.08 MHz
311.04 MHz
155.52 MHz
77.76 MHz
51.84 MHz
38.88 MHz
25.92 MHz
19.44 MHz
6.48 MHz
3
3
don’t-care
48E1
24E1
12E1
8E1
6E1
4E1
3E1
2E1
E1
1
0
1
/ T4_INPUT_FAIL
64E1
32E1
16E1
8E1
4E1
2E1
E1
Outputs on
2
96T1
48T1
24T1
16T1
12T1
8T1
6T1
4T1
3T1
2T1
T1
OUT3 & OUT7
64T1
32T1
16T1
8T1
4T1
2T1
T1
Output is disabled (output high).
Output is disabled (output low).
Output is disabled (output low) when the T4 selected input clock fails.
43
Output is enabled when the T4 selected input clock does not fail.
E3
E3
if Derived from T4 APLL Output
T3
T3
Output is disabled (output low).
Outputs on OUT8 & OUT9
(26 MHz X 2)
Output is enabled.
52 MHz
26 MHz
13 MHz
GSM
SYNCHRONOUS ETHERNET WAN PLL™
156.25 MHz
312.5 MHz
62.5 MHz
125 MHz
25 MHz
5 MHz
ETH
2, 4
(30.72 MHz X 10)
153.6 MHz
76.8 MHz
38.4 MHz
OBSAI
May 16, 2011
(40 MHz)
20 MHz
10 MHz
5 MHz
GPS