IDT82V3380AEQGBLANK IDT [Integrated Device Technology], IDT82V3380AEQGBLANK Datasheet - Page 8

• Manufacturer Part Number: IDT82V3380AEQGBLANK
• Manufacturer: IDT [Integrated Device Technology]

List of Figures
Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 21
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 23
Figure 5. External Fast Selection ................................................................................................................................................................................ 25
Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 26
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 32
Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 33
Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 44
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 44
Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 45
Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 45
Figure 13. 1 UI Late Frame Sync 2K/8K Pulse Input Signal Timing ............................................................................................................................ 45
Figure 14. On Target Frame Sync 2K/8K Pulse Input Signal Timing .......................................................................................................................... 45
Figure 15. Physical Connection Between Two Devices .............................................................................................................................................. 47
Figure 16. IDT82V3380A Power Decoupling Scheme ................................................................................................................................................. 49
Figure 17. Typical Application ...................................................................................................................................................................................... 50
Figure 18. EPROM Access Timing Diagram ............................................................................................................................................................... 52
Figure 19. Multiplexed Read Timing Diagram ............................................................................................................................................................. 53
Figure 20. Multiplexed Write Timing Diagram .............................................................................................................................................................. 54
Figure 21. Intel Read Timing Diagram ......................................................................................................................................................................... 55
Figure 22. Intel Write Timing Diagram ......................................................................................................................................................................... 56
Figure 23. Motorola Read Timing Diagram .................................................................................................................................................................. 57
Figure 24. Motorola Write Timing Diagram .................................................................................................................................................................. 58
Figure 25. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 59
Figure 26. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 59
Figure 27. Serial Write Timing Diagram ....................................................................................................................................................................... 60
Figure 28. JTAG Interface Timing Diagram ................................................................................................................................................................. 61
Figure 29. Assembly for Expose Pad thermal Release Path (Side View) ................................................................................................................. 153
Figure 30. 64 kHz + 8 kHz Signal Structure .............................................................................................................................................................. 155
Figure 31. 64 kHz + 8 kHz + 0.4 kHz Signal Structure .............................................................................................................................................. 155
Figure 32. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Input Level ................................................................................................................ 155
Figure 33. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Output Level ............................................................................................................. 155
Figure 34. AMI Input / Output Port Line Termination (Recommended) ..................................................................................................................... 156
Figure 35. Recommended PECL Input Port Line Termination .................................................................................................................................. 158
Figure 36. Recommended PECL Output Port Line Termination ................................................................................................................................ 158
Figure 37. Recommended LVDS Input Port Line Termination .................................................................................................................................. 160
Figure 38. Recommended LVDS Output Port Line Termination ................................................................................................................................ 160
Figure 39. Example of Single-Ended Signal to Drive Differential Input ..................................................................................................................... 161
Figure 40. Output Wander Generation ...................................................................................................................................................................... 165
Figure 41. Input / Output Clock Timing ...................................................................................................................................................................... 166
Figure 42. 100-Pin EQG Package Dimensions (a) (in Millimeters) ............................................................................................................................ 173
Figure 43. 100-Pin EQG Package Dimensions (b) (in Millimeters) ............................................................................................................................ 174
Figure 44. EQG100 Recommended Land Pattern with Exposed Pad (in Millimeters) .............................................................................................. 175
List of Figures
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May 16, 2011