s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 66

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

12 Power Conservation Modes
12.1
12.2
12.3
12.4
64
Standby Mode
Automatic Sleep Mode
Hardware RESET# Input Operation
Output Disable (OE#)
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input. The device enters the CMOS standby mode
when the CE# and RESET# inputs are both held at V
access time (t
erasure or programming, the device draws active current until the operation is completed. I
“DC Characteristics” represents the standby current specification
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous
mode. the device automatically enables this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Stan-
dard address access timings provide new data when addresses are changed. While in sleep mode,
output data is latched and always available to the system. While in synchronous mode, the auto-
matic sleep mode is disabled. Note that a new burst operation is required to provide new data.
I
specification.
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once the
device is ready to accept another command sequence to ensure data integrity.
When RESET# is held at V
is held at V
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
When the OE# input is at V
high impedance state.
CC6
in
DC Characteristics (CMOS Compatible)
IL
but not within V
CE
) for read access, before it is ready to read data. If the device is deselected during
SS
IH
A d v a n c e
± 0.2 V, the device draws CMOS standby current (I
S71WS-Nx0 Based MCPs
SS
, output from the device is disabled. The outputs are placed in the
± 0.2 V, the standby current is greater.
I n f o r m a t i o n
represents the automatic sleep mode current
RP
CC
, the device immediately terminates any
± 0.2 V. The device requires standard
S71WS-N_01_A4 September 15, 2005
CC4
). If RESET#
ACC
CC3
+ 20
in