s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 52

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

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may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation. Refer to
more details.
Note:
DQ5: Exceeded Timing Limits.
a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that
the program or erase cycle was not successfully completed. The device may output a “1” on DQ5
if the system tries to program a “1” to a location that was previously programmed to “0.” Only an
erase operation can change a “0” back to a “1.” Under this condition, the device halts the opera-
tion, and when the timing limit has been exceeded, DQ5 produces a “1.”Under both these
conditions, the system must write the reset command to return to the read mode (or to the erase-
suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator.
the system may read DQ3 to determine whether or not erasure has begun. (The sector erase
timer does not apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command. When the time-out
period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase
commands from the system can be assumed to be less than t
DQ3. See Sector Erase Command Sequence for more details.
After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and
then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands
(except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device
accepts additional sector erase commands. To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to and following each sub-sequent sector erase
command. If DQ3 is high on the second status check, the last command might not have been
accepted.
DQ1: Write to Buffer Abort.
Under these conditions DQ1 produces a “1”. The system must issue the Write to Buffer Abort
Reset command sequence to return the device to reading array data. See Write Buffer Program-
ming Operation for more details.
When verifying the status of a write operation (embedded program/erase) of a memory bank,
DQ6 and DQ2 toggle between high and low states in a series of consecutive and con-tiguous
status read cycles. In order for this toggling behavior to be properly observed, the consecu-
tive status bit reads must not be interleaved with read accesses to other memory banks. If it
is not possible to temporarily prevent reads to other memory banks, then it is recommended
to use the DQ7 status bit as the alternative method of determining the active or inactive sta-
tus of the write operation.
Table 10.20
shows the status of DQ3 relative to the other status bits.
A d v a n c e
S71WS-Nx0 Based MCPs
DQ1 indicates whether a Write to Buffer operation was aborted.
DQ5 indicates whether the program or erase time has exceeded
I n f o r m a t i o n
After writing a sector erase command sequence,
SEA
, the system need not monitor
S71WS-N_01_A4 September 15, 2005
Figure 10.6
for