s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 31

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

September 15, 2005 S71WS-N_01_A4
Delay X Clocks
Word
Word
Table 10.6 Address/Boundary Crossing Latency (S29WS256N @ 54MHz)
0
1
2
3
0
1
2
3
Table 10.7 Address/Boundary Crossing Latency (S29WS128N)
Wait States
Wait States
Yes
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
A d v a n c e
5 ws
5 ws
5 ws
5 ws
Boundary?
Crossing
D0
D1
D2
D3
D0
D1
D2
D3
No
I n f o r m a t i o n
1 ws
1 ws
D1
D2
D3
D1
D2
D3
S71WS-Nx0 Based MCPs
Additional Latency Due to Starting
Write Set Configuration Register
Address, Clock Frequency, and
Figure 10.2 Synchronous Read
No
Address 555h, Data AAh
Address 2AAh, Data 55h
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
1 ws
1 ws
1 ws
1 ws
D2
D3
D2
D3
Write Unlock Cycles:
Load Initial Address
Boundary Crossing
Read Initial Data
Read Next Data
RD = DQ[15:0]
RD = DQ[15:0]
Address = RA
Wait X Clocks:
End of Data?
Completed
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D3
D3
Yes
Cycle
Cycle
1 ws
1 ws
1 ws
1 ws
D4
D4
D4
D4
Note: Setup Configuration Register parameters
D5
D5
D5
D5
D4
D4
D4
D4
Refer to the Latency tables.
Unlock Cycle 1
Unlock Cycle 2
Command Cycle
CR = Configuration Register Bits CR15-CR0
RA = Read Address
RD = Read Data
D6
D6
D6
D6
D5
D5
D5
D5
D7
D7
D7
D7
D6
D6
D6
D6
D8
D8
D8
D8
D7
D7
D7
D7
29