s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 177

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

September 15, 2005 S71WS-N_01_A4
Symbol
t
t
t
t
t
CSHP
t
t
BMH
WES
WEH
BMS
BS
BH
48.3.2.1 Write Timings
Latency = 5, Burst Length = 4, WP = Low enable (OE# = V
CS# Toggling Consecutive Burst Write
Notes:
1.
2.
3.
4.
5.
LB#, UB#
CLK
ADV#
Address
CS#
WE#
Data in
WAIT#
The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
D2 is masked by UB# and LB#.
Burst Cycle Time (t
BEADV
Min
5
5
5
7
7
5
5
should be met.
A d v a n c e
Speed
t
CSS(B)
WL
WH
High-Z
t
WZ
AS(B)
or t
): Data available (driven by Latency-1 clock)
t
): Data don’t care (driven by CS# high going edge)
WES
BC
AWL
Valid
Valid
Figure 48.6 Timing Waveform of Burst Write Cycle (1)
) should not be over 2.5µs.
0
t
WL
Max
): Data not available (driven by CS# low going edge or ADV# low going edge)
—
—
—
—
—
—
—
T
t
ADVS
t
ADVH
Table 48.5 Burst Write AC Characteristics
1
t
t
AH(B)
WEH
I n f o r m a t i o n
Latency 5
S71WS-Nx0 Based MCPs
2
t
WH
Don’t Ca re
Units
ns
3
t
BC
t
t
BS
DS
D0
4
t
DHC
Symbol
t
t
t
t
t
WHP
t
t
DHC
WH
WL
WZ
BH
DS
D1
5
t
BMS
D2
6
t
D3
BMH
7
t
DHC
IH
Min
t
—
—
—
, MRS# = V
WHP
5
5
3
t
t
CSHP
BEADV
8
t
WZ
Valid
Valid
Speed
9
t
WL
10
IH
).
Latency 5
Max
10
12
—
—
—
7
11
t
WH
12
D0
13
Units
ns
175