s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 123

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

September 15, 2005 S71WS-N_01_A4
31.3.2
UB#, LB#
Asynchronous Write Timing Waveform
Asynchronous Write Cycle - WE# Controlled
Notes:
1.
2.
3.
4.
5.
6.
Note:
CS#
Data out
Address
WE#
Data in
A write occurs during the overlap (t
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t
beginning of write to the end of write.
t
t
t
going high.
In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
Condition for continuous write operation over 50 times: t
CW
AS
WR
Symbol
t
t
t
t
t
t
is measured from the address valid to the beginning of write.
WC
CW
AW
BW
WP
is measured from the CS# going low to the end of write.
is measured from the end of write to the address change. t
WP(min)
A d v a n c e
= 70ns for continuous write operation over 50 times.
t
AS
55 (note 1)
Table 31.3 Asynchronous Write AC Characteristics
Min
70
60
60
60
Figure 31.4 Timing Waveform Of Write Cycle
t
Speed
t
t
BW
High-Z
AW
CW
I n f o r m a t i o n
S71WS-Nx0 Based MCPs
t
WC
t
WP
WP
) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
t
DW
Dat a Valid
Max
—
—
—
—
—
t
WR
t
t
DH
WHP
Units
WP(min)
ns
t
t
AS
CSHP
WR
=70ns.
is applied in case a write ends with CS# or WE#
Symbol
t
t
t
CHSP
t
t
t
t
t
WR
DW
AW
CW
BW
DH
AS
t
t
WC
WP
t
DW
Dat a Valid
High- Z
Min
30
10
0
0
0
Speed
WP
t
WR
is measured from the
t
Max
DH
—
—
—
—
Units
ns
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