s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 55

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

10.9
10.10 Software Reset
September 15, 2005 S71WS-N_01_A4
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the device
is ready to accept another command sequence.
When RESET# is held at V
at V
RESET# may be tied to the system reset circuitry which enables the system to read the boot-up
firmware from the Flash memory upon a system reset.
See
Software reset is part of the command set (see
read mode and must be used for the following conditions:
1.
2.
3.
4.
5.
Note: Base = Base Address.
The following is a C source code example of using the reset function. Refer to the Spansion
Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general
information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */
The following are additional points to consider when using the reset command:
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
This command resets the banks to the read and address bits are ignored.
Reset commands are ignored once erasure has begun until the operation is complete.
Once programming begins, the device ignores reset commands until the operation is com-
plete
The reset command may be written between the cycles in a program command sequence be-
fore programming begins (prior to the third cycle). This resets the bank to which the system
was writing to the read mode.
If the program command sequence is written to a bank that is in the Erase Suspend mode,
writing the reset command returns that bank to the erase-suspend-read mode.
The reset command may be also written during an Autoselect command sequence.
If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
IL
Figures 14.5
to exit Autoselect mode
when DQ5 goes high during write status operation that indicates program or erase cycle was
not successfully completed
exit sector lock/unlock operation.
to return to erase-suspend-read mode if the device was previously in Erase Suspend mode.
after any aborted operations
, but not at V
Reset Command
A d v a n c e
Cycle
and
SS
Table 10.21 Reset LLD Function = lld_ResetCmd)
, the standby current is greater.
14.12
SS
I n f o r m a t i o n
for timing diagrams.
, the device draws CMOS standby current (I
S71WS-Nx0 Based MCPs
Operation
Write
Table
Base + xxxh
Byte Address
RP
15.1) that also returns the device to array
, the device immediately terminates any
Word Address
Base + xxxh
CC4
). If RESET# is held
00F0h
Data
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