s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 113

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

24 Synchronous Burst Operation
24.1
24.2 Synchronous Burst Write Operation
September 15, 2005 S71WS-N_01_A4
Synchronous Burst Read Operation
Burst mode operations enable the system to get high performance read and write operation. The
address to be accessed is latched on the rising edge of clock or ADV# (whichever occurs first).
CS# should be setup before the address latch. During this first clock rising edge, WE# indicates
whether the operation is going to be a Read (WE# High) or a Write (WE# Low).
For the optimized Burst Mode of each system, the system should determine how many clock cy-
cles are required for the first data of each burst access (Latency Count), how many words the
device outputs during an access (Burst Length) and which type of burst operation (Burst Type:
Linear or Interleave) is needed. The Wait Polarity should also be determined (See
The Synchronous Burst Read command is implemented when the clock rising is detected during
the ADV# low pulse. ADV# and CS# should be set up before the clock rising. During the Read
command, WE# should be held in V
are allowed, but the burst operation starts from the first clock rising. The first data will be out
with Latency count and t
The Synchronous Burst Write command is implemented when the clock rising is detected during
the ADV# and WE# low pulse. ADV#, WE# and CS# should be set up before the clock rising. The
multiple clock risings (during the low ADV# period) are allowed but, the burst operation starts
from the first clock rising. The first data will be written in the Latency clock with t
A d v a n c e
Note:
Note:
UB#, LB#
UB#, LB#
Data Out
WAIT#
Data in
WAIT#
ADV#
ADV#
CD
Addr.
WE#
CS#
OE#
Addr .
CS#
CLK
CLK
Latency 5, BL 4, WP: Low Enable
.
Latency 5, BL 4, WP: Low Enable
I n f o r m a t i o n
Figure 24.2 Synchronous Burst Write
Figure 24.1 Synchronous Burst Read
S71WS-Nx0 Based MCPs
0
0
1
IH
1
2
. The multiple clock risings (during the low ADV# period)
3
2
4
3
4
5
6
5
6
7
7
8
8
9
10
9
10
11
11
12
13
12
13
14
DS
Table
.
22.2).
111