s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 104

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

17 Pin Description
102
I/O0-I/O15
Pin Name
A0-A21
WAIT#
MRS#
ADV#
WE#
V
V
CS#
OE#
UB#
DNU
LB#
CLK
V
V
CCQ
SSQ
CC
SS
Address 0 ~ Address 21
Data Inputs / Outputs
Upper Byte (I/O
Lower Byte (I/O
Core Voltage Source
Core Ground Source
Valid Data Indicator
I/O Voltage Source
I/O Ground Source
Mode Register set
Output Enable
Address Valid
Write Enable
Do Not Use
Chip Select
Function
Clock
8~15
0~7
A d v a n c e
S71WS-Nx0 Based MCPs
)
)
Input/Output
Output
Power
Power
Input
Type
GND
GND
—
I n f o r m a t i o n
Commands, Data are referenced to CLK
Address valid from ADV# falling edge to ADV# rising edge
MRS# enables Mode Register to be set.
Addresses are loaded as Mode setting is Low
CS# enables the chip to start operating when Low
CS# disables the chip and puts it into standby mode when High
CS# stops burst operating.during burst operation when High
OE# enables the chip to output the data when Low
WE# enables the chip to start writing the data when Low
UB# (or LB#) enables upper byte (or lower byte) to be
operated when Low
Valid addresses input when ADV# is low.
Mode setting inputs during MRS# Low.
Depending on UB# or LB# status, word (16-bit,
UB#, and LB# low) data, upper byte (8-bit, UB#
low & LB# high) data or lower byte (8-bit, LB# low,
and UB# high) data is loaded
Power supply for cells and circuits except for I/O buffer circuits
Power supply for I/O buffer circuits
Ground for cells and circuits except for I/O buffer circuits
Ground for I/O buffer circuits
WAIT# indicates that output data is invalid when Low
Description
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S71WS-N_01_A4 September 15, 2005