s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 124

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

122
31.3.2.1 Write Cycle 2
MRS# = V
Notes:
1.
2.
3.
4.
5.
Note:
UB#, LB#
CS#
Address
WE#
Data in
Data out
A write occurs during the overlap (t
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t
beginning of write to the end of write.
t
t
t
going high.
In asynchronous write cycle, Clock, ADV# and WAIT# signals are ignored.
CW
AS
WR
Symbol
t
t
t
t
t
t
is measured from the address valid to the beginning of write.
WC
CW
AW
BW
WP
is measured from the CS# going low to the end of write.
is measured from the end of write to the address change. t
WP(min)
Table 31.4 Asynchronous Write AC Characteristics (UB# & LB# Controlled)
IH
, OE# = V
= 70ns for continuous write operation over 50 times.
55 (note 1)
IH
Figure 31.5 Timing Waveform of Write Cycle(2)
Min
70
60
60
60
, WAIT# = High-Z, UB# & LB# Controlled
Speed
A d v a n c e
S71WS-Nx0 Based MCPs
High-Z
WP
) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
t
AS
Max
—
—
—
—
—
I n f o r m a t i o n
Units
ns
t
AW
t
t
WP
WC
t
t
CW
BW
WR
is applied in case a write ends with CS# or WE#
Symbol
t
DW
t
t
Dat a Valid
t
t
WR
DW
DH
AS
t
WR
t
DH
Min
30
0
0
0
S71WS-N_01_A4 September 15, 2005
High- Z
Speed
WP
is measured from the
Max
—
—
—
—
Units
ns