s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 23

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

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September 15, 2005 S71WS-N_01_A4
Input/Output Descriptions & Logic Symbol
Table 6.1
DQ15–DQ0
Symbol
RESET#
A23–A0
AVD#
WE#
WP#
CE#
OE#
RDY
CLK
ACC
RFU
V
V
NC
CC
SS
identifies the input and output package connections provided on the device.
A d v a n c e
No Connect
Reserved
Supply
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
Address lines for WS256N (A22-A0 for WS128).
Data input/output.
Chip Enable. Asynchronous relative to CLK.
Output Enable. Asynchronous relative to CLK.
Write Enable.
Device Power Supply.
Ground.
Not connected internally.
Ready. Indicates when valid burst data is ready to be read.
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK
increment the internal address counter. Should be at V
mode.
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst
mode, causes starting address to be latched at the next active clock edge.
When high, device ignores address inputs.
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect. At V
Should be at V
Acceleration Input. At V
unlock bypass mode. At V
all other conditions.
Reserved for future use (see MCP look-ahead pinout for use with MCP).
I n f o r m a t i o n
Table 6.1 Input/Output Descriptions
S71WS-Nx0 Based MCPs
IH
for all other conditions.
IL
, disables program and erase functions in the four outermost sectors.
HH
IL
, accelerates programming; automatically places device in
, disables all program and erase functions. Should be at V
Description
IL
or V
IH
while in asynchronous
IH
for
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