s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 10

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

Figures
8
Figure 7.1
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 11.1
Figure 11.2
Figure 11.3
Figure 14.1
Figure 14.2
Figure 14.3
Figure 14.4
Figure 14.5
Figure 14.6
Figure 14.7
Figure 14.8
Figure 14.9
Figure 14.10 Linear Burst with RDY Set One Cycle Before Data ..................................................................................76
Figure 14.11 Asynchronous Mode Read...................................................................................................................77
Figure 14.12 Reset Timings...................................................................................................................................78
Figure 14.13 Chip/Sector Erase Operation Timings ...................................................................................................80
Figure 14.14 Program Operation Timing Using AVD# ................................................................................................81
Figure 14.15 Program Operation Timing Using CLK in Relationship to AVD#.................................................................82
Figure 14.16 Accelerated Unlock Bypass Programming Timing ...................................................................................83
Figure 14.17 Data# Polling Timings (During Embedded Algorithm) .............................................................................83
Figure 14.18 Toggle Bit Timings (During Embedded Algorithm) ..................................................................................84
Figure 14.19 Synchronous Data Polling Timings/Toggle Bit Timings ............................................................................84
Figure 14.20 DQ2 vs. DQ6 ....................................................................................................................................85
Figure 14.21 Latency with Boundary Crossing when Frequency > 66 MHz....................................................................85
Figure 14.22 Latency with Boundary Crossing into Program/Erase Bank ......................................................................86
Figure 14.23 Example of Wait States Insertion ........................................................................................................87
Figure 14.24 Back-to-Back Read/Write Cycle Timings ...............................................................................................88
Figure 20.1
Figure 20.2
Figure 22.1
Figure 22.2
Figure 23.1
Figure 23.2
Figure 24.1
Figure 24.2
Figure 25.1
Figure 25.2
Figure 26.1
Figure 31.1
Figure 31.2
Figure 31.3
Figure 31.4
Figure 31.5
Figure 31.6
Figure 31.7
Figure 31.8
Figure 31.9
S29WS-N Block Diagram....................................................................................................................22
Synchronous/Asynchronous State Diagram...........................................................................................27
Synchronous Read ............................................................................................................................29
Single Word Program.........................................................................................................................35
Write Buffer Programming Operation ...................................................................................................39
Sector Erase Operation ......................................................................................................................41
Write Operation Status Flowchart ........................................................................................................48
Advanced Sector Protection/Unprotection .............................................................................................55
PPB Program/Erase Algorithm .............................................................................................................58
Lock Register Program Algorithm.........................................................................................................61
Maximum Negative Overshoot Waveform .............................................................................................68
Maximum Positive Overshoot Waveform ...............................................................................................68
Test Setup .......................................................................................................................................69
Input Waveforms and Measurement Levels ...........................................................................................70
V
CLK Characterization .........................................................................................................................72
CLK Synchronous Burst Mode Read......................................................................................................74
8-word Linear Burst with Wrap Around.................................................................................................75
8-word Linear Burst without Wrap Around ............................................................................................75
Power Up Timing............................................................................................................................. 104
Standby Mode State Machines .......................................................................................................... 104
Pin MRS Timing Waveform (OE# = V
Software MRS Timing Waveform ....................................................................................................... 109
Asynchronous 4-Page Read .............................................................................................................. 110
Asynchronous Write......................................................................................................................... 110
Synchronous Burst Read .................................................................................................................. 111
Synchronous Burst Write.................................................................................................................. 111
Latency Configuration (Read)............................................................................................................ 112
WAIT# and Read/Write Latency Control ............................................................................................. 113
PAR Mode Execution and Exit............................................................................................................ 115
PAR Mode Execution and Exit............................................................................................................ 117
Timing Waveform Of Asynchronous Read Cycle ................................................................................... 119
Timing Waveform Of Page Read Cycle................................................................................................ 120
Timing Waveform Of Write Cycle ....................................................................................................... 121
Timing Waveform of Write Cycle(2) ................................................................................................... 122
Timing Waveform Of Write Cycle (Address Latch Type) ........................................................................ 123
Timing Waveform Of Write Cycle (Low ADV# Type) ............................................................................. 124
Timing Waveform Of Write Cycle (Low ADV# Type) ............................................................................. 125
Timing Waveform Of Write Cycle (Low ADV# Type) ............................................................................. 126
CC
Power-up Diagram ......................................................................................................................70
A d v a n c e
S71WS-Nx0 Based MCPs
IH
) ............................................................................................. 108
I n f o r m a t i o n
S71WS-N_01_A4 September 15, 2005