s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 167

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

September 15, 2005 S71WS-N_01_A4
47.3.2.1 Write Cycle (Address Latch Type)
MRS# = V
Notes:
1.
2.
3.
4.
5.
Notes:
1.
2.
UB#, LB#
A write occurs during the overlap (t
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for word operation.
A write ends at the earliest transition when CS# goes high or WE# goes high. The t
of write to the end of write.
t
t
t
Clock input does not have any affect to the write operation if the parameter t
Address Latch Type, WE# Controlled.
t
CLK
CS#
Data out
ADV#
Address
WE#
Data in
AW
CW
BW
Symbol
WP(min)
t
t
t
CSS(A)
t
AH(A)
AS(A)
t
t
ADV
CW
AW
is measured from the address valid to the end of write. In this address latch type write timing, t
is measured from the UB# and LB# going low to the end of write.
is measured from the CS# going low to the end of write.
Table 47.5 Asynchronous Write in Synchronous Mode AC Characteristics
= 70ns for continuous write operation over 50 times.
IH
A d v a n c e
t
AS(A)
, OE# = V
Figure 47.6 Timing Waveform Of Write Cycle (Address Latch Type)
Valid
0
Min
10
60
60
t
AS
7
0
7
Speed
t
t
CSS(A)
ADV
1
t
AH(A)
IH
Read Latency 5
, WAIT# = High-Z, WE# Controlled
Max
High- Z
—
—
—
—
—
—
2
I n f o r m a t i o n
S71WS-Nx0 Based MCPs
t
WLRL
WP
3
) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
Units
ns
t
4
CW
t
t
AW
BW
5
t
WP
Symbol
t
t
WLRL
t
t
t
t
DW
BW
WP
DH
AS
6
7
t
8
DW
Dat a Valid
55 (note 2)
WLRL
High-Z
Min
9
60
30
1
0
0
is met.
Speed
WP
10
t
DH
is measured from the beginning
11
12
Max
—
—
—
—
—
—
WC
is same as t
13
clock
Units
14
ns
ns
165
AW
.