s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 108
s71ws256nc0bawa30
Manufacturer Part Number
s71ws256nc0bawa30
Description
Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
Manufacturer
Meet Spansion Inc.
Datasheet
1.S71WS256NC0BAWA30.pdf
(188 pages)
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106
Notes:
1.
2.
3.
4.
5.
Deselected
Deselected
Output
Disabled
Outputs
Disabled
Read
Command
Lower Byte
Read
Upper Byte
Read
Word Read
Write
Command
Lower Byte
Write
Upper Byte
Write
Word Write
Mode
Register
Set
X must be low or high state.
X means “Don’t care” (can be low, high or toggling).
WAIT# is the device output signal and does not have any affect on the mode definition. Please refer to each timing
diagram for WAIT# pin function.
The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid,
implement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst
write mode.
The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So
the transition from Synchronous burst write operation to Asynchronous write operation is prohibited.
Mode
Table 21.3 Synchronous Burst Read & Synchronous Burst Write Mode(A15/A14 = 1/0)
CS# MRS#
H
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
(Note
(Note
(Note
(Note
(Note
OE#
X
X
H
X
X
X
H
H
H
H
L
L
L
1)
1)
1)
1)
1)
A d v a n c e
S71WS-Nx0 Based MCPs
L
L
(Note
(Note
(Note
(Note
(Note
(Note
WE#
or
or
X
X
H
X
H
H
H
H
X
X
X
1)
1)
1)
1)
1)
1)
(Note
(Note
I n f o r m a t i o n
LB#
X
X
X
H
X
H
H
L
L
L
L
L
1)
1)
(Note
(Note
UB#
H
H
H
X
X
X
X
L
L
L
L
L
1)
1)
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z
High-Z High-Z
High-Z
High-Z High-Z
I/O
D
D
D
D
OUT
OUT
IN
IN
0-7
High-Z
High-Z
I/O
D
D
D
D
OUT
OUT
IN
IN
8-15
S71WS-N_01_A4 September 15, 2005
(Note
(Note
(Note
(Note
CLK
X
X
X
X
2)
2)
2)
2)
(Note
(Note
ADV#
X
X
H
H
H
H
H
H
H
H
2)
2)
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Power
PAR
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