s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 152

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

38 Mode Register Setting Operation
38.1
150
Mode Register Set (MRS)
The device has several modes:
Partial Array Refresh (PAR) mode is defined through the Mode Register Set (MRS) option. The MRS
option also defines burst length, burst type, wait polarity and latency count at synchronous burst
read/write mode.
The mode register stores the data for controlling the various operation modes of the pSRAM. It
programs Partial Array Refresh (PAR), burst length, burst type, latency count and various vendor
specific options to make pSRAM useful for a variety of different applications. The default values
of mode register are defined, therefore when the reserved address is input, the device runs at
default modes.
The mode register is written by driving CS#, ADV#, WE#, UB#, LB# and MRS# to V
OE# to V
the fields of functions. The PAR field uses A0–A4, Burst Length field uses A5–A7, Burst Type uses
A8, Latency Count uses A9–A11, Wait Polarity uses A13, Operation Mode uses A14–A15 and
Driver Strength uses A16–A17.
Refer to the Table below for detailed Mode Register Settings. A18–A22 addresses are “Don’t care”
in the Mode Register Setting.
Note:
Length), PAR (Partial Array Refresh), PARA (Partial Array Refresh Array), PARS (Partial Array Refresh Size), RFU (Reserved
for Future Use).
A13
A17
0
1
Function
0
0
1
Address
Asynchronous Page Read mode
Asynchronous Write mode
Synchronous Burst Read mode
Synchronous Burst Write mode
Standby mode and Partial Array Refresh (PAR) mode.
Low Enable (note 1)
WAIT# Polarity
DS (Driver Strength), MS (Mode Select), WP (Wait Polarity), Latency (Latency Count), BT (Burst Type), BL (Burst
A16
0
1
0
High Enable
IH
Driver Strength
during valid addressing. The mode register is divided into various fields depending on
WP
A17 – A16
Table 38.1 Mode Register Setting According to Field of Function
DS
Full Drive (note 1)
1/2 Drive
1/4 Drive
DS
A12
0
1
A15 – A14
MS
RFU
(note 1)
A d v a n c e
Must
RFU
S71WS-Nx0 Based MCPs
—
Table 38.2 Mode Register Set
A13
WP
A11 A10 A9 Latency A8
A15
0
0
0
0
0
0
1
Latency Count
0
0
1
1
RFU
A12
A14
0
1
0
0
1
0
1
I n f o r m a t i o n
A11 – A19
Latency
3
4
5
6
Async. 4 Page Read / Async. Write (note 1)
0
1
Sync. Burst Read / Sync. Burst Write
A8
BT
Linear (note 1)
Burst Type
Sync. Burst Read / Async. Write
Interleave
Mode Select
A7 – A5
BT
BL
MS
A7 A6 A5
0
0
1
1
A4 – A3
S71WS-N_01_A4 September 15, 2005
PAR
1
1
0
1
Burst Length
0
1
0
1
PARA
16 word (note 1)
A2
Full (256 word)
IL
and driving
4 word
8 word
BL
A1 – A0
PARS